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[interchange] Site pin conflicts in RAM test #287

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gatecat opened this issue May 4, 2021 · 3 comments
Closed

[interchange] Site pin conflicts in RAM test #287

gatecat opened this issue May 4, 2021 · 3 comments

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@gatecat
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gatecat commented May 4, 2021

Run make test-fpga_interchange-ram_basys3-dcp in nextpnr and open the DCP in Vivado. There are routing issues (nets in yellow rather than green), report_route_status reports the following:

  GLOBAL_LOGIC0
    Unrouted Nodes (not associated with pins or ports):
      BRAM_L_X6Y30/BRAM_FIFO18_WEBWE4
      BRAM_L_X6Y30/BRAM_FIFO18_WEBWE5
      BRAM_L_X6Y30/BRAM_FIFO18_WEBWE6
      BRAM_L_X6Y30/BRAM_FIFO18_WEBWE7
  GLOBAL_LOGIC1
    Unrouted Nodes (not associated with pins or ports):
      BRAM_L_X6Y30/BRAM_FIFO18_REGCLKARDRCLK
      BRAM_L_X6Y30/BRAM_FIFO18_REGCLKB
    Conflicts with Site Pins: BRAM_L_X6Y30/BRAM_FIFO18_REGCLKB (RAMB18_X0Y12/REGCLKB)
  ram.rdclk
    Conflicts with Site Pins: BRAM_L_X6Y30/BRAM_FIFO18_REGCLKB (RAMB18_X0Y12/REGCLKB)

An illustration of some of the routing problems:

Screenshot from 2021-05-04 14-20-01

It appears like the cell-bel pin mapping isn't correct.

Design files:
ram_basys3.zip

cc @acomodi - are the examples in nextpnr still supposed to work, or in practice are they deprecated and I should be using fpga-interchange-tests instead?
@gatecat gatecat mentioned this issue May 4, 2021
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@gatecat
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gatecat commented May 4, 2021

This is affecting fpga-interchange-tests as well, actually. It is probably a good idea to get CI with Vivado up and running sooner rather than later....

@gatecat
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gatecat commented May 4, 2021

Oops, my RapidWright was out of date. With that fixed it works fine.

@gatecat gatecat closed this as completed May 4, 2021
@acomodi
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acomodi commented May 5, 2021

@gatecat I think that the tests in nextpnr are still valid from a PnR point of view so that we know that everything is fine there, but the validation of these should happen in fpga-interchange-tests.

I'll soon add the DRC validation step for xc7 in fpga-interchange-tests so we can catch these kinds of issues.

In general I'd say that we should have all the tests in nextpnr working (aka valid DCP are generated) and a way to frequently check this in fpga-interchange-tests. The problem is that at the moment the nextpnr, interchange-schema and python-interchange need to be manually updated to the latest versions, and here a bot might be required to get to update regularly and automatically the versions of the various tools, such that, if some change either in one of the tools causes the validation step to fail, we can catch it ASAP.

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@acomodi @gatecat