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1 parent a23df42 commit 1e7783aCopy full SHA for 1e7783a
build.py
@@ -58,7 +58,7 @@ def main():
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"jtag_tap_spartan6.v", "lm32_itlb.v", "lm32_dtlb.v")
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plat.add_sources(os.path.join("verilog", "lm32"), "lm32_config.v")
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- plat.build_cmdline(soc.get_fragment(), clock_domains=soc.crg.get_clock_domains())
+ plat.build_cmdline(soc, clock_domains=soc.crg.get_clock_domains())
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if __name__ == "__main__":
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main()
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