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base repository: m-labs/migen
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head repository: m-labs/migen
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compare: b016a60b8539
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  • 2 commits
  • 2 files changed
  • 1 contributor

Commits on Jul 15, 2013

  1. genlib/fifo: add test bench

    Sebastien Bourdeauducq committed Jul 15, 2013
    Copy the full SHA
    7083764 View commit details
  2. lasmibus: fix master locking

    Sebastien Bourdeauducq committed Jul 15, 2013
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    b016a60 View commit details
Showing with 39 additions and 4 deletions.
  1. +14 −4 migen/bus/lasmibus.py
  2. +25 −0 migen/genlib/fifo.py
18 changes: 14 additions & 4 deletions migen/bus/lasmibus.py
Original file line number Diff line number Diff line change
@@ -66,13 +66,23 @@ def __init__(self, controllers, nmasters, cba_shift):
controller_selected = [1]*nmasters
master_req_acks = [0]*nmasters
master_dat_acks = [0]*nmasters
for nb in range(nbanks):
rrs = [roundrobin.RoundRobin(nmasters, roundrobin.SP_CE) for n in range(nbanks)]
self.submodules += rrs
for nb, rr in enumerate(rrs):
bank = getattr(controller, "bank"+str(nb))

# for each master, determine if another bank locks it
master_locked = []
for nm, master in enumerate(self.masters):
locked = 0
for other_nb, other_rr in enumerate(rrs):
if other_nb != nb:
other_bank = getattr(controller, "bank"+str(other_nb))
locked = locked | (other_bank.lock & (other_rr.grant == nm))
master_locked.append(locked)

# arbitrate
rr = roundrobin.RoundRobin(nmasters, roundrobin.SP_CE)
self.submodules += rr
bank_selected = [cs & (ba == nb) for cs, ba in zip(controller_selected, m_ba)]
bank_selected = [cs & (ba == nb) & ~locked for cs, ba, locked in zip(controller_selected, m_ba, master_locked)]
bank_requested = [bs & master.stb for bs, master in zip(bank_selected, self.masters)]
self.comb += [
rr.request.eq(Cat(*bank_requested)),
25 changes: 25 additions & 0 deletions migen/genlib/fifo.py
Original file line number Diff line number Diff line change
@@ -129,3 +129,28 @@ def __init__(self, width_or_layout, depth):
rdport.adr.eq(consume.q_binary[:-1]),
self.dout_bits.eq(rdport.dat_r)
]

class _SyncFIFOTB(Module):
def __init__(self):
self.submodules.dut = SyncFIFO([("a", 32), ("b", 32)], 2)

self.sync += [
If(self.dut.we & self.dut.writable,
self.dut.din.a.eq(self.dut.din.a + 1),
self.dut.din.b.eq(self.dut.din.b + 2)
)
]

def do_simulation(self, s):
s.wr(self.dut.we, s.cycle_counter % 4 == 0)
s.wr(self.dut.re, s.cycle_counter % 3 == 0)
print("readable: {0} re: {1} data: {2}/{3}".format(s.rd(self.dut.readable),
s.rd(self.dut.re),
s.rd(self.dut.dout.a), s.rd(self.dut.dout.b)))

def _main():
from migen.sim.generic import Simulator
Simulator(_SyncFIFOTB()).run(20)

if __name__ == "__main__":
_main()