Skip to content
Permalink

Comparing changes

Choose two branches to see what’s changed or to start a new pull request. If you need to, you can also or learn more about diff comparisons.

Open a pull request

Create a new pull request by comparing changes across two branches. If you need to, you can also . Learn more about diff comparisons here.
base repository: m-labs/misoc
Failed to load repositories. Confirm that selected base ref is valid, then try again.
Loading
base: e4de5a0c9dbd
Choose a base ref
...
head repository: m-labs/misoc
Failed to load repositories. Confirm that selected head ref is valid, then try again.
Loading
compare: 5e2e9338d21c
Choose a head ref
  • 9 commits
  • 32 files changed
  • 1 contributor

Commits on Feb 27, 2015

  1. 5
    Copy the full SHA
    b817cf4 View commit details
  2. move memtest to sdram

    enjoy-digital committed Feb 27, 2015
    Copy the full SHA
    9f636f7 View commit details
  3. Copy the full SHA
    9814001 View commit details
  4. 1
    Copy the full SHA
    be0eb8d View commit details
  5. Copy the full SHA
    367db26 View commit details
  6. 11
    Copy the full SHA
    07b9cab View commit details
  7. sdram: import dfi, lasmibus, wishbone2lasmi from Migen in sdram/bus dir

    We will maybe move things, but at least it's in MiSoC now
    enjoy-digital committed Feb 27, 2015
    Copy the full SHA
    e07e124 View commit details
  8. targets: fix MiniSoC

    enjoy-digital committed Feb 27, 2015
    Copy the full SHA
    b031c5e View commit details
  9. bios: we can now use -Ot with_rom True on targets to force bios imple…

    …mentation in integrated rom (can speed up debug we don't want to reflash SPI or NOR flash)
    enjoy-digital committed Feb 27, 2015
    2
    Copy the full SHA
    5e2e933 View commit details
39 changes: 17 additions & 22 deletions make.py
Original file line number Diff line number Diff line change
@@ -7,6 +7,7 @@
from migen.fhdl import simplify

from misoclib.gensoc import cpuif
from misoclib.cpu import CPU
from misoclib.sdram.phy import initsequence

from misoc_import import misoc_import
@@ -121,7 +122,7 @@ def _get_args():
actions["build-bios"] = True
if not actions["load-bitstream"]:
actions["flash-bitstream"] = True
if not hasattr(soc, "init_bios_memory"):
if not soc.with_rom:
actions["flash-bios"] = True
if actions["build-bitstream"] and hasattr(soc, "init_bios_memory"):
actions["build-bios"] = True
@@ -144,28 +145,30 @@ def _get_args():
*/
""".format(platform_name, args.target, top_class.__name__, soc.cpu_type)
if isinstance(soc.cpu_or_bridge, CPU):
cpu_mak = cpuif.get_cpu_mak(soc.cpu_type)
write_to_file("software/include/generated/cpu.mak", cpu_mak)
linker_output_format = cpuif.get_linker_output_format(soc.cpu_type)
write_to_file("software/include/generated/output_format.ld", linker_output_format)

linker_regions = cpuif.get_linker_regions(soc.cpu_memory_regions)
linker_regions = cpuif.get_linker_regions(soc.memory_regions)
write_to_file("software/include/generated/regions.ld", boilerplate + linker_regions)
try:
flash_boot_address = soc.flash_boot_address
except AttributeError:
flash_boot_address = None
mem_header = cpuif.get_mem_header(soc.cpu_memory_regions, flash_boot_address)
write_to_file("software/include/generated/mem.h", boilerplate + mem_header)
csr_header = cpuif.get_csr_header(soc.cpu_csr_regions, soc.interrupt_map)
write_to_file("software/include/generated/csr.h", boilerplate + csr_header)

for sdram_phy in ["sdrphy", "ddrphy"]:
if hasattr(soc, sdram_phy):
sdram_phy_header = initsequence.get_sdram_phy_header(getattr(soc, sdram_phy))
write_to_file("software/include/generated/sdram_phy.h", boilerplate + sdram_phy_header)
try:
flash_boot_address = soc.flash_boot_address
except AttributeError:
flash_boot_address = None
mem_header = cpuif.get_mem_header(soc.memory_regions, flash_boot_address)
write_to_file("software/include/generated/mem.h", boilerplate + mem_header)
csr_header = cpuif.get_csr_header(soc.csr_regions, soc.interrupt_map)
write_to_file("software/include/generated/csr.h", boilerplate + csr_header)

if actions["build-csr-csv"]:
csr_csv = cpuif.get_csr_csv(soc.cpu_csr_regions)
csr_csv = cpuif.get_csr_csv(soc.csr_regions)
write_to_file(args.csr_csv, csr_csv)

if actions["build-bios"]:
@@ -174,16 +177,8 @@ def _get_args():
raise OSError("BIOS build failed")

if actions["build-bitstream"]:
if hasattr(soc, "init_bios_memory"):
with open("software/bios/bios.bin", "rb") as bios_file:
bios_data = []
while True:
w = bios_file.read(4)
if not w:
break
bios_data.append(struct.unpack(">I", w)[0])
soc.init_bios_memory(bios_data)

if soc.with_rom:
soc.init_rom()
for decorator in args.decorate:
soc = getattr(simplify, decorator)(soc)
build_kwargs = dict((k, autotype(v)) for k, v in args.build_option)
@@ -209,4 +204,4 @@ def _get_args():
if actions["flash-bios"]:
prog = platform.create_programmer()
prog.set_flash_proxy_dir(args.flash_proxy_dir)
prog.flash(soc.cpu_reset_address, "software/bios/bios.bin")
prog.flash(soc.cpu_reset_address, soc.cpu_boot_file)
4 changes: 4 additions & 0 deletions misoclib/cpu/__init__.py
Original file line number Diff line number Diff line change
@@ -0,0 +1,4 @@
from migen.fhdl.std import *

class CPU(Module):
pass
4 changes: 3 additions & 1 deletion misoclib/lm32/__init__.py → misoclib/cpu/lm32/__init__.py
Original file line number Diff line number Diff line change
@@ -3,7 +3,9 @@
from migen.fhdl.std import *
from migen.bus import wishbone

class LM32(Module):
from misoclib.cpu import CPU

class LM32(CPU):
def __init__(self, platform, eba_reset):
self.ibus = i = wishbone.Interface()
self.dbus = d = wishbone.Interface()
Original file line number Diff line number Diff line change
@@ -3,7 +3,9 @@
from migen.fhdl.std import *
from migen.bus import wishbone

class MOR1KX(Module):
from misoclib.cpu import CPU

class MOR1KX(CPU):
def __init__(self, platform, reset_pc):
self.ibus = i = wishbone.Interface()
self.dbus = d = wishbone.Interface()
50 changes: 25 additions & 25 deletions misoclib/framebuffer/phy.py
Original file line number Diff line number Diff line change
@@ -51,20 +51,20 @@ def __init__(self, pack_factor):
# This assumes a 50MHz base clock
class _Clocking(Module, AutoCSR):
def __init__(self, pads_vga, pads_dvi):
self._r_cmd_data = CSRStorage(10)
self._r_send_cmd_data = CSR()
self._r_send_go = CSR()
self._r_status = CSRStatus(4)
self._cmd_data = CSRStorage(10)
self._send_cmd_data = CSR()
self._send_go = CSR()
self._status = CSRStatus(4)

self.clock_domains.cd_pix = ClockDomain(reset_less=True)
if pads_dvi is not None:
self._r_pll_reset = CSRStorage()
self._r_pll_adr = CSRStorage(5)
self._r_pll_dat_r = CSRStatus(16)
self._r_pll_dat_w = CSRStorage(16)
self._r_pll_read = CSR()
self._r_pll_write = CSR()
self._r_pll_drdy = CSRStatus()
self._pll_reset = CSRStorage()
self._pll_adr = CSRStorage(5)
self._pll_dat_r = CSRStatus(16)
self._pll_dat_w = CSRStorage(16)
self._pll_read = CSR()
self._pll_write = CSR()
self._pll_drdy = CSRStatus()

self.clock_domains.cd_pix2x = ClockDomain(reset_less=True)
self.clock_domains.cd_pix10x = ClockDomain(reset_less=True)
@@ -92,31 +92,31 @@ def __init__(self, pads_vga, pads_dvi):
self.comb += transmitting.eq(remaining_bits != 0)
sr = Signal(10)
self.sync += [
If(self._r_send_cmd_data.re,
If(self._send_cmd_data.re,
remaining_bits.eq(10),
sr.eq(self._r_cmd_data.storage)
sr.eq(self._cmd_data.storage)
).Elif(transmitting,
remaining_bits.eq(remaining_bits - 1),
sr.eq(sr[1:])
)
]
self.comb += [
pix_progdata.eq(transmitting & sr[0]),
pix_progen.eq(transmitting | self._r_send_go.re)
pix_progen.eq(transmitting | self._send_go.re)
]

# enforce gap between commands
busy_counter = Signal(max=14)
busy = Signal()
self.comb += busy.eq(busy_counter != 0)
self.sync += If(self._r_send_cmd_data.re,
self.sync += If(self._send_cmd_data.re,
busy_counter.eq(13)
).Elif(busy,
busy_counter.eq(busy_counter - 1)
)

mult_locked = Signal()
self.comb += self._r_status.status.eq(Cat(busy, pix_progdone, pix_locked, mult_locked))
self.comb += self._status.status.eq(Cat(busy, pix_progdone, pix_locked, mult_locked))

# Clock multiplication and buffering
if pads_dvi is None:
@@ -133,10 +133,10 @@ def __init__(self, pads_vga, pads_dvi):
pll_clk2 = Signal()
locked_async = Signal()
pll_drdy = Signal()
self.sync += If(self._r_pll_read.re | self._r_pll_write.re,
self._r_pll_drdy.status.eq(0)
self.sync += If(self._pll_read.re | self._pll_write.re,
self._pll_drdy.status.eq(0)
).Elif(pll_drdy,
self._r_pll_drdy.status.eq(1)
self._pll_drdy.status.eq(1)
)
self.specials += [
Instance("PLL_ADV",
@@ -151,13 +151,13 @@ def __init__(self, pads_vga, pads_dvi):
o_CLKOUT0=pll_clk0, o_CLKOUT1=pll_clk1, o_CLKOUT2=pll_clk2,
o_CLKFBOUT=clkfbout, i_CLKFBIN=clkfbout,
o_LOCKED=pll_locked,
i_RST=~pix_locked | self._r_pll_reset.storage,
i_RST=~pix_locked | self._pll_reset.storage,

i_DADDR=self._r_pll_adr.storage,
o_DO=self._r_pll_dat_r.status,
i_DI=self._r_pll_dat_w.storage,
i_DEN=self._r_pll_read.re | self._r_pll_write.re,
i_DWE=self._r_pll_write.re,
i_DADDR=self._pll_adr.storage,
o_DO=self._pll_dat_r.status,
i_DI=self._pll_dat_w.storage,
i_DEN=self._pll_read.re | self._pll_write.re,
i_DWE=self._pll_write.re,
o_DRDY=pll_drdy,
i_DCLK=ClockSignal()),
Instance("BUFPLL", p_DIVIDE=5,
Loading