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base repository: m-labs/artiq
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head repository: m-labs/artiq
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compare: 4e5320be285e
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  • 2 commits
  • 2 files changed
  • 2 contributors

Commits on Feb 28, 2015

  1. adapt code to MiSoC's changes

    @enjoy-digital @sbourdeauducq
    enjoy-digital authored and sbourdeauducq committed Feb 28, 2015
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    9cf8db2 View commit details

  2. Merge branch 'master' of https://github.com/m-labs/artiq

    @sbourdeauducq
    sbourdeauducq committed Feb 28, 2015

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    This commit is not signed, but one or more authors requires that any commit attributed to them is signed.
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    4e5320b View commit details
Showing with 3 additions and 2 deletions.
  1. +1 −1 soc/targets/artiq_kc705.py
  2. +2 −1 soc/targets/artiq_ppro.py
2 changes: 1 addition & 1 deletion soc/targets/artiq_kc705.py
View file
Original file line number Diff line number Diff line change
@@ -3,7 +3,7 @@
from migen.bank import wbgen
from mibuild.generic_platform import *

from misoclib import gpio
from misoclib.cpu.peripherals import gpio
from targets.kc705 import BaseSoC

from artiqlib import rtio, ad9858
3 changes: 2 additions & 1 deletion soc/targets/artiq_ppro.py
View file
Original file line number Diff line number Diff line change
@@ -3,7 +3,7 @@
from migen.bank import wbgen
from mibuild.generic_platform import *

from misoclib import gpio
from misoclib.cpu.peripherals import gpio
from targets.ppro import BaseSoC

from artiqlib import rtio, ad9858
@@ -97,6 +97,7 @@ def __init__(self, platform, cpu_type="or1k",
with_test_gen=False, **kwargs):
BaseSoC.__init__(self, platform,
cpu_type=cpu_type, ramcon_type=ramcon_type,
with_l2=with_l2,
**kwargs)
platform.add_extension(_tester_io)