m-labs · Feb 27, 2015 · Feb 27, 2015
Showing with 125 additions and 20 deletions.

+10 −2 make.py

+3 −18 misoclib/gensoc/__init__.py

+112 −0 targets/de0nano.py
diff --git a/make.py b/make.py
@@ -124,7 +124,7 @@ def _get_args():
 			actions["flash-bitstream"] = True
 		if not soc.with_rom:
 			actions["flash-bios"] = True
-	if actions["build-bitstream"] and hasattr(soc, "init_bios_memory"):
+	if actions["build-bitstream"] and soc.with_rom:
 		actions["build-bios"] = True
 	if actions["build-bios"]:
 		actions["build-headers"] = True
@@ -178,7 +178,15 @@ def _get_args():
 
 	if actions["build-bitstream"]:
 		if soc.with_rom:
-			soc.init_rom()
+			with open(soc.cpu_boot_file, "rb") as boot_file:
+				boot_data = []
+				while True:
+					w = boot_file.read(4)
+					if not w:
+						break
+					boot_data.append(struct.unpack(">I", w)[0])
+			soc.init_rom(boot_data)
+
 		for decorator in args.decorate:
 			soc = getattr(simplify, decorator)(soc)
 		build_kwargs = dict((k, autotype(v)) for k, v in args.build_option)

diff --git a/misoclib/gensoc/__init__.py b/misoclib/gensoc/__init__.py
@@ -39,7 +39,7 @@ class GenSoC(Module):
 	def __init__(self, platform, clk_freq, cpu_or_bridge=None,
 				with_cpu=True, cpu_type="lm32", cpu_reset_address=0x00000000,
 							   cpu_boot_file="software/bios/bios.bin",
-				with_rom=False, rom_size=0x8000, rom_init_now=False,
+				with_rom=False, rom_size=0x8000,
 				with_sram=True, sram_size=4096,
 				with_sdram=False, sdram_size=64*1024,
 				with_csr=True, csr_data_width=8, csr_address_width=14,
@@ -57,7 +57,6 @@ def __init__(self, platform, clk_freq, cpu_or_bridge=None,
 
 		self.with_rom = with_rom
 		self.rom_size = rom_size
-		self.rom_init_now = rom_init_now
 
 		self.with_sram = with_sram
 		self.sram_size = sram_size
@@ -93,8 +92,6 @@ def __init__(self, platform, clk_freq, cpu_or_bridge=None,
 			if with_rom:
 				self.submodules.rom = wishbone.SRAM(rom_size, read_only=True)
 				self.register_mem("rom", self.mem_map["rom"], self.rom.bus, rom_size)
-				if rom_init_now:
-					self.init_rom()
 
 			if with_sram:
 				self.submodules.sram = wishbone.SRAM(sram_size)
@@ -118,20 +115,8 @@ def __init__(self, platform, clk_freq, cpu_or_bridge=None,
 			if with_timer:
 				self.submodules.timer0 = timer.Timer()
 
-	def init_rom(self, filename=None):
-		if filename is None:
-			filename = self.cpu_boot_file
-		filename_ext = os.path.splitext(filename)[1]
-		if filename_ext != ".bin":
-			raise ValueError("rom_init only supports .bin files")
-		with open(filename, "rb") as boot_file:
-			boot_data = []
-			while True:
-				w = boot_file.read(4)
-				if not w:
-					break
-				boot_data.append(struct.unpack(">I", w)[0])
-		self.rom.mem.init = boot_data
+	def init_rom(self, data):
+		self.rom.mem.init = data
 
 	def add_wb_master(self, wbm):
 		if self.finalized:

diff --git a/targets/de0nano.py b/targets/de0nano.py
@@ -0,0 +1,112 @@
+from migen.fhdl.std import *
+from migen.bus import wishbone
+
+from misoclib import uart, gpio, sdram
+from misoclib.sdram.phy import gensdrphy
+from misoclib.gensoc import SDRAMSoC
+
+class _PLL(Module):
+	def __init__(self, period_in, name, phase_shift, operation_mode):
+		self.clk_in = Signal()
+		self.clk_out = Signal()
+
+		self.specials += Instance("ALTPLL",
+			p_bandwidth_type = "AUTO",
+			p_clk0_divide_by = 1,
+			p_clk0_duty_cycle = 50,
+			p_clk0_multiply_by = 2,
+			p_clk0_phase_shift = "{}".format(str(phase_shift)),
+			p_compensate_clock = "CLK0",
+			p_inclk0_input_frequency = int(period_in*1000),
+			p_intended_device_family = "Cyclone IV E",
+			p_lpm_hint = "CBX_MODULE_PREFIX={}_pll".format(name),
+			p_lpm_type = "altpll",
+			p_operation_mode = operation_mode,
+			i_inclk=self.clk_in,
+			o_clk=self.clk_out,
+			i_areset=0,
+			i_clkena=0x3f,
+			i_clkswitch=0,
+			i_configupdate=0,
+			i_extclkena=0xf,
+			i_fbin=1,
+			i_pfdena=1,
+			i_phasecounterselect=0xf,
+			i_phasestep=1,
+			i_phaseupdown=1,
+			i_pllena=1,
+			i_scanaclr=0,
+			i_scanclk=0,
+			i_scanclkena=1,
+			i_scandata=0,
+			i_scanread=0,
+			i_scanwrite=0
+		)
+
+class _CRG(Module):
+	def __init__(self, platform):
+		self.clock_domains.cd_sys = ClockDomain()
+		self.clock_domains.cd_sys_ps = ClockDomain()
+		self.clock_domains.cd_por = ClockDomain(reset_less=True)
+
+		clk50 = platform.request("clk50")
+
+		sys_pll = _PLL(20, "sys", 0, "NORMAL")
+		self.submodules += sys_pll
+		self.comb += [
+			sys_pll.clk_in.eq(clk50),
+			self.cd_sys.clk.eq(sys_pll.clk_out)
+		]
+
+		sdram_pll = _PLL(20, "sdram", -3000, "ZERO_DELAY_BUFFER")
+		self.submodules += sdram_pll
+		self.comb += [
+			sdram_pll.clk_in.eq(clk50),
+			self.cd_sys_ps.clk.eq(sdram_pll.clk_out)
+		]
+
+		# Power on Reset (vendor agnostic)
+		rst_n = Signal()
+		self.sync.por += rst_n.eq(1)
+		self.comb += [
+			self.cd_por.clk.eq(self.cd_sys.clk),
+			self.cd_sys.rst.eq(~rst_n),
+			self.cd_sys_ps.rst.eq(~rst_n)
+		]
+
+		self.comb += platform.request("sdram_clock").eq(self.cd_sys_ps.clk)
+
+class BaseSoC(SDRAMSoC):
+	default_platform = "de0nano"
+
+	def __init__(self, platform, **kwargs):
+		SDRAMSoC.__init__(self, platform,
+			clk_freq=100*1000000,
+			with_rom=True,
+			**kwargs)
+
+		sdram_geom = sdram.GeomSettings(
+			bank_a=2,
+			row_a=13,
+			col_a=9
+		)
+
+		sdram_timing = sdram.TimingSettings(
+			tRP=self.ns(20),
+			tRCD=self.ns(20),
+			tWR=self.ns(20),
+			tWTR=2,
+			tREFI=self.ns(7800, False),
+			tRFC=self.ns(70),
+
+			req_queue_size=8,
+			read_time=32,
+			write_time=16
+		)
+
+		self.submodules.crg = _CRG(platform)
+
+		self.submodules.sdrphy = gensdrphy.GENSDRPHY(platform.request("sdram"))
+		self.register_sdram_phy(self.sdrphy.dfi, self.sdrphy.phy_settings, sdram_geom, sdram_timing)
+
+default_subtarget = BaseSoC