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targets: do not implement sdram if already provided by SoC (allow use…
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… of -Ot with_sdram = True)
enjoy-digital committed Mar 6, 2015
1 parent 52f1c45 commit 2b9397f
Showing 6 changed files with 121 additions and 111 deletions.
5 changes: 3 additions & 2 deletions misoclib/soc/sdram.py
Original file line number Diff line number Diff line change
@@ -70,6 +70,7 @@ def register_sdram_phy(self, phy, sdram_geom, sdram_timing):
raise NotImplementedError("Unsupported SDRAM width of {} > 32".format(sdram_width))

def do_finalize(self):
if not self._sdram_phy_registered:
raise FinalizeError("Need to call SDRAMSoC.register_sdram_phy()")
if not self.with_sdram:
if not self._sdram_phy_registered:
raise FinalizeError("Need to call SDRAMSoC.register_sdram_phy()")
SoC.do_finalize(self)
43 changes: 22 additions & 21 deletions targets/de0nano.py
Original file line number Diff line number Diff line change
@@ -87,28 +87,29 @@ def __init__(self, platform, **kwargs):
with_rom=True,
**kwargs)

sdram_geom = sdram.GeomSettings(
bank_a=2,
row_a=13,
col_a=9
)

sdram_timing = sdram.TimingSettings(
tRP=self.ns(20),
tRCD=self.ns(20),
tWR=self.ns(20),
tWTR=2,
tREFI=self.ns(7800, False),
tRFC=self.ns(70),

req_queue_size=8,
read_time=32,
write_time=16
)

self.submodules.crg = _CRG(platform)

self.submodules.sdrphy = gensdrphy.GENSDRPHY(platform.request("sdram"))
self.register_sdram_phy(self.sdrphy, sdram_geom, sdram_timing)
if not self.with_sdram:
sdram_geom = sdram.GeomSettings(
bank_a=2,
row_a=13,
col_a=9
)

sdram_timing = sdram.TimingSettings(
tRP=self.ns(20),
tRCD=self.ns(20),
tWR=self.ns(20),
tWTR=2,
tREFI=self.ns(7800, False),
tRFC=self.ns(70),

req_queue_size=8,
read_time=32,
write_time=16
)

self.submodules.sdrphy = gensdrphy.GENSDRPHY(platform.request("sdram"))
self.register_sdram_phy(self.sdrphy, sdram_geom, sdram_timing)

default_subtarget = BaseSoC
39 changes: 20 additions & 19 deletions targets/kc705.py
Original file line number Diff line number Diff line change
@@ -80,25 +80,26 @@ def __init__(self, platform, **kwargs):

self.submodules.crg = _CRG(platform)

sdram_geom = sdram.GeomSettings(
bank_a=3,
row_a=16,
col_a=10
)
sdram_timing = sdram.TimingSettings(
tRP=self.ns(15),
tRCD=self.ns(15),
tWR=self.ns(15),
tWTR=2,
tREFI=self.ns(7800, False),
tRFC=self.ns(70),

req_queue_size=8,
read_time=32,
write_time=16
)
self.submodules.ddrphy = k7ddrphy.K7DDRPHY(platform.request("ddram"), memtype="DDR3")
self.register_sdram_phy(self.ddrphy, sdram_geom, sdram_timing)
if not self.with_sdram:
sdram_geom = sdram.GeomSettings(
bank_a=3,
row_a=16,
col_a=10
)
sdram_timing = sdram.TimingSettings(
tRP=self.ns(15),
tRCD=self.ns(15),
tWR=self.ns(15),
tWTR=2,
tREFI=self.ns(7800, False),
tRFC=self.ns(70),

req_queue_size=8,
read_time=32,
write_time=16
)
self.submodules.ddrphy = k7ddrphy.K7DDRPHY(platform.request("ddram"), memtype="DDR3")
self.register_sdram_phy(self.ddrphy, sdram_geom, sdram_timing)

spiflash_pads = platform.request("spiflash")
spiflash_pads.clk = Signal()
55 changes: 30 additions & 25 deletions targets/mlabs_video.py
Original file line number Diff line number Diff line change
@@ -38,26 +38,35 @@ def __init__(self, platform, **kwargs):
cpu_reset_address=0x00180000,
**kwargs)

sdram_geom = sdram.GeomSettings(
bank_a=2,
row_a=13,
col_a=10
)
sdram_timing = sdram.TimingSettings(
tRP=self.ns(15),
tRCD=self.ns(15),
tWR=self.ns(15),
tWTR=2,
tREFI=self.ns(7800, False),
tRFC=self.ns(70),

req_queue_size=8,
read_time=32,
write_time=16
)
self.submodules.ddrphy = s6ddrphy.S6DDRPHY(platform.request("ddram"), memtype="DDR",
rd_bitslip=0, wr_bitslip=3, dqs_ddr_alignment="C1")
self.register_sdram_phy(self.ddrphy, sdram_geom, sdram_timing)
self.submodules.crg = mxcrg.MXCRG(_MXClockPads(platform), self.clk_freq)

if not self.with_sdram:
sdram_geom = sdram.GeomSettings(
bank_a=2,
row_a=13,
col_a=10
)
sdram_timing = sdram.TimingSettings(
tRP=self.ns(15),
tRCD=self.ns(15),
tWR=self.ns(15),
tWTR=2,
tREFI=self.ns(7800, False),
tRFC=self.ns(70),

req_queue_size=8,
read_time=32,
write_time=16
)
self.submodules.ddrphy = s6ddrphy.S6DDRPHY(platform.request("ddram"), memtype="DDR",
rd_bitslip=0, wr_bitslip=3, dqs_ddr_alignment="C1")
self.register_sdram_phy(self.ddrphy, sdram_geom, sdram_timing)


self.comb += [
self.ddrphy.clk4x_wr_strb.eq(self.crg.clk4x_wr_strb),
self.ddrphy.clk4x_rd_strb.eq(self.crg.clk4x_rd_strb)
]

self.submodules.norflash = norflash16.NorFlash16(platform.request("norflash"),
self.ns(110), self.ns(50))
@@ -67,11 +76,7 @@ def __init__(self, platform, **kwargs):
if not self.with_rom:
self.register_rom(self.norflash.bus)

self.submodules.crg = mxcrg.MXCRG(_MXClockPads(platform), self.clk_freq)
self.comb += [
self.ddrphy.clk4x_wr_strb.eq(self.crg.clk4x_wr_strb),
self.ddrphy.clk4x_rd_strb.eq(self.crg.clk4x_rd_strb)
]

platform.add_platform_command("""
INST "mxcrg/wr_bufpll" LOC = "BUFPLL_X0Y2";
INST "mxcrg/rd_bufpll" LOC = "BUFPLL_X0Y3";
53 changes: 27 additions & 26 deletions targets/pipistrello.py
Original file line number Diff line number Diff line change
@@ -96,32 +96,33 @@ def __init__(self, platform, **kwargs):

self.submodules.crg = _CRG(platform, clk_freq)

sdram_geom = sdram.GeomSettings(
bank_a=2,
row_a=13,
col_a=10
)
sdram_timing = sdram.TimingSettings(
tRP=self.ns(15),
tRCD=self.ns(15),
tWR=self.ns(15),
tWTR=2,
tREFI=self.ns(64*1000*1000/8192, False),
tRFC=self.ns(72),
req_queue_size=8,
read_time=32,
write_time=16
)
self.submodules.ddrphy = s6ddrphy.S6DDRPHY(platform.request("sdram"),
"LPDDR", rd_bitslip=1, wr_bitslip=3, dqs_ddr_alignment="C1")
self.comb += [
self.ddrphy.clk4x_wr_strb.eq(self.crg.clk4x_wr_strb),
self.ddrphy.clk4x_rd_strb.eq(self.crg.clk4x_rd_strb),
]
platform.add_platform_command("""
PIN "BUFG.O" CLOCK_DEDICATED_ROUTE = FALSE;
""")
self.register_sdram_phy(self.ddrphy, sdram_geom, sdram_timing)
if not self.with_sdram:
sdram_geom = sdram.GeomSettings(
bank_a=2,
row_a=13,
col_a=10
)
sdram_timing = sdram.TimingSettings(
tRP=self.ns(15),
tRCD=self.ns(15),
tWR=self.ns(15),
tWTR=2,
tREFI=self.ns(64*1000*1000/8192, False),
tRFC=self.ns(72),
req_queue_size=8,
read_time=32,
write_time=16
)
self.submodules.ddrphy = s6ddrphy.S6DDRPHY(platform.request("sdram"),
"LPDDR", rd_bitslip=1, wr_bitslip=3, dqs_ddr_alignment="C1")
self.comb += [
self.ddrphy.clk4x_wr_strb.eq(self.crg.clk4x_wr_strb),
self.ddrphy.clk4x_rd_strb.eq(self.crg.clk4x_rd_strb),
]
platform.add_platform_command("""
PIN "BUFG.O" CLOCK_DEDICATED_ROUTE = FALSE;
""")
self.register_sdram_phy(self.ddrphy, sdram_geom, sdram_timing)

self.submodules.spiflash = spiflash.SpiFlash(platform.request("spiflash4x"), dummy=11, div=2)
self.flash_boot_address = 0x180000
37 changes: 19 additions & 18 deletions targets/ppro.py
Original file line number Diff line number Diff line change
@@ -73,24 +73,25 @@ def __init__(self, platform, **kwargs):

self.submodules.crg = _CRG(platform, clk_freq)

sdram_geom = sdram.GeomSettings(
bank_a=2,
row_a=12,
col_a=8
)
sdram_timing = sdram.TimingSettings(
tRP=self.ns(15),
tRCD=self.ns(15),
tWR=self.ns(14),
tWTR=2,
tREFI=self.ns(64*1000*1000/4096, False),
tRFC=self.ns(66),
req_queue_size=8,
read_time=32,
write_time=16
)
self.submodules.sdrphy = gensdrphy.GENSDRPHY(platform.request("sdram"))
self.register_sdram_phy(self.sdrphy, sdram_geom, sdram_timing)
if not self.with_sdram:
sdram_geom = sdram.GeomSettings(
bank_a=2,
row_a=12,
col_a=8
)
sdram_timing = sdram.TimingSettings(
tRP=self.ns(15),
tRCD=self.ns(15),
tWR=self.ns(14),
tWTR=2,
tREFI=self.ns(64*1000*1000/4096, False),
tRFC=self.ns(66),
req_queue_size=8,
read_time=32,
write_time=16
)
self.submodules.sdrphy = gensdrphy.GENSDRPHY(platform.request("sdram"))
self.register_sdram_phy(self.sdrphy, sdram_geom, sdram_timing)

self.submodules.spiflash = spiflash.SpiFlash(platform.request("spiflash2x"), dummy=4, div=6)
self.flash_boot_address = 0x70000

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