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enjoy-digitalenjoy-digital
committedMar 6, 2015
targets: do not implement sdram if already provided by SoC (allow use of -Ot with_sdram = True)
·
0.120.1
1 parent 52f1c45 commit 2b9397f

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6 files changed

+121
-111
lines changed

6 files changed

+121
-111
lines changed
 

‎misoclib/soc/sdram.py

+3-2
Original file line numberDiff line numberDiff line change
@@ -70,6 +70,7 @@ def register_sdram_phy(self, phy, sdram_geom, sdram_timing):
7070
raise NotImplementedError("Unsupported SDRAM width of {} > 32".format(sdram_width))
7171

7272
def do_finalize(self):
73-
if not self._sdram_phy_registered:
74-
raise FinalizeError("Need to call SDRAMSoC.register_sdram_phy()")
73+
if not self.with_sdram:
74+
if not self._sdram_phy_registered:
75+
raise FinalizeError("Need to call SDRAMSoC.register_sdram_phy()")
7576
SoC.do_finalize(self)

‎targets/de0nano.py

+22-21
Original file line numberDiff line numberDiff line change
@@ -87,28 +87,29 @@ def __init__(self, platform, **kwargs):
8787
with_rom=True,
8888
**kwargs)
8989

90-
sdram_geom = sdram.GeomSettings(
91-
bank_a=2,
92-
row_a=13,
93-
col_a=9
94-
)
95-
96-
sdram_timing = sdram.TimingSettings(
97-
tRP=self.ns(20),
98-
tRCD=self.ns(20),
99-
tWR=self.ns(20),
100-
tWTR=2,
101-
tREFI=self.ns(7800, False),
102-
tRFC=self.ns(70),
103-
104-
req_queue_size=8,
105-
read_time=32,
106-
write_time=16
107-
)
108-
10990
self.submodules.crg = _CRG(platform)
11091

111-
self.submodules.sdrphy = gensdrphy.GENSDRPHY(platform.request("sdram"))
112-
self.register_sdram_phy(self.sdrphy, sdram_geom, sdram_timing)
92+
if not self.with_sdram:
93+
sdram_geom = sdram.GeomSettings(
94+
bank_a=2,
95+
row_a=13,
96+
col_a=9
97+
)
98+
99+
sdram_timing = sdram.TimingSettings(
100+
tRP=self.ns(20),
101+
tRCD=self.ns(20),
102+
tWR=self.ns(20),
103+
tWTR=2,
104+
tREFI=self.ns(7800, False),
105+
tRFC=self.ns(70),
106+
107+
req_queue_size=8,
108+
read_time=32,
109+
write_time=16
110+
)
111+
112+
self.submodules.sdrphy = gensdrphy.GENSDRPHY(platform.request("sdram"))
113+
self.register_sdram_phy(self.sdrphy, sdram_geom, sdram_timing)
113114

114115
default_subtarget = BaseSoC

‎targets/kc705.py

+20-19
Original file line numberDiff line numberDiff line change
@@ -80,25 +80,26 @@ def __init__(self, platform, **kwargs):
8080

8181
self.submodules.crg = _CRG(platform)
8282

83-
sdram_geom = sdram.GeomSettings(
84-
bank_a=3,
85-
row_a=16,
86-
col_a=10
87-
)
88-
sdram_timing = sdram.TimingSettings(
89-
tRP=self.ns(15),
90-
tRCD=self.ns(15),
91-
tWR=self.ns(15),
92-
tWTR=2,
93-
tREFI=self.ns(7800, False),
94-
tRFC=self.ns(70),
95-
96-
req_queue_size=8,
97-
read_time=32,
98-
write_time=16
99-
)
100-
self.submodules.ddrphy = k7ddrphy.K7DDRPHY(platform.request("ddram"), memtype="DDR3")
101-
self.register_sdram_phy(self.ddrphy, sdram_geom, sdram_timing)
83+
if not self.with_sdram:
84+
sdram_geom = sdram.GeomSettings(
85+
bank_a=3,
86+
row_a=16,
87+
col_a=10
88+
)
89+
sdram_timing = sdram.TimingSettings(
90+
tRP=self.ns(15),
91+
tRCD=self.ns(15),
92+
tWR=self.ns(15),
93+
tWTR=2,
94+
tREFI=self.ns(7800, False),
95+
tRFC=self.ns(70),
96+
97+
req_queue_size=8,
98+
read_time=32,
99+
write_time=16
100+
)
101+
self.submodules.ddrphy = k7ddrphy.K7DDRPHY(platform.request("ddram"), memtype="DDR3")
102+
self.register_sdram_phy(self.ddrphy, sdram_geom, sdram_timing)
102103

103104
spiflash_pads = platform.request("spiflash")
104105
spiflash_pads.clk = Signal()

‎targets/mlabs_video.py

+30-25
Original file line numberDiff line numberDiff line change
@@ -38,26 +38,35 @@ def __init__(self, platform, **kwargs):
3838
cpu_reset_address=0x00180000,
3939
**kwargs)
4040

41-
sdram_geom = sdram.GeomSettings(
42-
bank_a=2,
43-
row_a=13,
44-
col_a=10
45-
)
46-
sdram_timing = sdram.TimingSettings(
47-
tRP=self.ns(15),
48-
tRCD=self.ns(15),
49-
tWR=self.ns(15),
50-
tWTR=2,
51-
tREFI=self.ns(7800, False),
52-
tRFC=self.ns(70),
53-
54-
req_queue_size=8,
55-
read_time=32,
56-
write_time=16
57-
)
58-
self.submodules.ddrphy = s6ddrphy.S6DDRPHY(platform.request("ddram"), memtype="DDR",
59-
rd_bitslip=0, wr_bitslip=3, dqs_ddr_alignment="C1")
60-
self.register_sdram_phy(self.ddrphy, sdram_geom, sdram_timing)
41+
self.submodules.crg = mxcrg.MXCRG(_MXClockPads(platform), self.clk_freq)
42+
43+
if not self.with_sdram:
44+
sdram_geom = sdram.GeomSettings(
45+
bank_a=2,
46+
row_a=13,
47+
col_a=10
48+
)
49+
sdram_timing = sdram.TimingSettings(
50+
tRP=self.ns(15),
51+
tRCD=self.ns(15),
52+
tWR=self.ns(15),
53+
tWTR=2,
54+
tREFI=self.ns(7800, False),
55+
tRFC=self.ns(70),
56+
57+
req_queue_size=8,
58+
read_time=32,
59+
write_time=16
60+
)
61+
self.submodules.ddrphy = s6ddrphy.S6DDRPHY(platform.request("ddram"), memtype="DDR",
62+
rd_bitslip=0, wr_bitslip=3, dqs_ddr_alignment="C1")
63+
self.register_sdram_phy(self.ddrphy, sdram_geom, sdram_timing)
64+
65+
66+
self.comb += [
67+
self.ddrphy.clk4x_wr_strb.eq(self.crg.clk4x_wr_strb),
68+
self.ddrphy.clk4x_rd_strb.eq(self.crg.clk4x_rd_strb)
69+
]
6170

6271
self.submodules.norflash = norflash16.NorFlash16(platform.request("norflash"),
6372
self.ns(110), self.ns(50))
@@ -67,11 +76,7 @@ def __init__(self, platform, **kwargs):
6776
if not self.with_rom:
6877
self.register_rom(self.norflash.bus)
6978

70-
self.submodules.crg = mxcrg.MXCRG(_MXClockPads(platform), self.clk_freq)
71-
self.comb += [
72-
self.ddrphy.clk4x_wr_strb.eq(self.crg.clk4x_wr_strb),
73-
self.ddrphy.clk4x_rd_strb.eq(self.crg.clk4x_rd_strb)
74-
]
79+
7580
platform.add_platform_command("""
7681
INST "mxcrg/wr_bufpll" LOC = "BUFPLL_X0Y2";
7782
INST "mxcrg/rd_bufpll" LOC = "BUFPLL_X0Y3";

‎targets/pipistrello.py

+27-26
Original file line numberDiff line numberDiff line change
@@ -96,32 +96,33 @@ def __init__(self, platform, **kwargs):
9696

9797
self.submodules.crg = _CRG(platform, clk_freq)
9898

99-
sdram_geom = sdram.GeomSettings(
100-
bank_a=2,
101-
row_a=13,
102-
col_a=10
103-
)
104-
sdram_timing = sdram.TimingSettings(
105-
tRP=self.ns(15),
106-
tRCD=self.ns(15),
107-
tWR=self.ns(15),
108-
tWTR=2,
109-
tREFI=self.ns(64*1000*1000/8192, False),
110-
tRFC=self.ns(72),
111-
req_queue_size=8,
112-
read_time=32,
113-
write_time=16
114-
)
115-
self.submodules.ddrphy = s6ddrphy.S6DDRPHY(platform.request("sdram"),
116-
"LPDDR", rd_bitslip=1, wr_bitslip=3, dqs_ddr_alignment="C1")
117-
self.comb += [
118-
self.ddrphy.clk4x_wr_strb.eq(self.crg.clk4x_wr_strb),
119-
self.ddrphy.clk4x_rd_strb.eq(self.crg.clk4x_rd_strb),
120-
]
121-
platform.add_platform_command("""
122-
PIN "BUFG.O" CLOCK_DEDICATED_ROUTE = FALSE;
123-
""")
124-
self.register_sdram_phy(self.ddrphy, sdram_geom, sdram_timing)
99+
if not self.with_sdram:
100+
sdram_geom = sdram.GeomSettings(
101+
bank_a=2,
102+
row_a=13,
103+
col_a=10
104+
)
105+
sdram_timing = sdram.TimingSettings(
106+
tRP=self.ns(15),
107+
tRCD=self.ns(15),
108+
tWR=self.ns(15),
109+
tWTR=2,
110+
tREFI=self.ns(64*1000*1000/8192, False),
111+
tRFC=self.ns(72),
112+
req_queue_size=8,
113+
read_time=32,
114+
write_time=16
115+
)
116+
self.submodules.ddrphy = s6ddrphy.S6DDRPHY(platform.request("sdram"),
117+
"LPDDR", rd_bitslip=1, wr_bitslip=3, dqs_ddr_alignment="C1")
118+
self.comb += [
119+
self.ddrphy.clk4x_wr_strb.eq(self.crg.clk4x_wr_strb),
120+
self.ddrphy.clk4x_rd_strb.eq(self.crg.clk4x_rd_strb),
121+
]
122+
platform.add_platform_command("""
123+
PIN "BUFG.O" CLOCK_DEDICATED_ROUTE = FALSE;
124+
""")
125+
self.register_sdram_phy(self.ddrphy, sdram_geom, sdram_timing)
125126

126127
self.submodules.spiflash = spiflash.SpiFlash(platform.request("spiflash4x"), dummy=11, div=2)
127128
self.flash_boot_address = 0x180000

‎targets/ppro.py

+19-18
Original file line numberDiff line numberDiff line change
@@ -73,24 +73,25 @@ def __init__(self, platform, **kwargs):
7373

7474
self.submodules.crg = _CRG(platform, clk_freq)
7575

76-
sdram_geom = sdram.GeomSettings(
77-
bank_a=2,
78-
row_a=12,
79-
col_a=8
80-
)
81-
sdram_timing = sdram.TimingSettings(
82-
tRP=self.ns(15),
83-
tRCD=self.ns(15),
84-
tWR=self.ns(14),
85-
tWTR=2,
86-
tREFI=self.ns(64*1000*1000/4096, False),
87-
tRFC=self.ns(66),
88-
req_queue_size=8,
89-
read_time=32,
90-
write_time=16
91-
)
92-
self.submodules.sdrphy = gensdrphy.GENSDRPHY(platform.request("sdram"))
93-
self.register_sdram_phy(self.sdrphy, sdram_geom, sdram_timing)
76+
if not self.with_sdram:
77+
sdram_geom = sdram.GeomSettings(
78+
bank_a=2,
79+
row_a=12,
80+
col_a=8
81+
)
82+
sdram_timing = sdram.TimingSettings(
83+
tRP=self.ns(15),
84+
tRCD=self.ns(15),
85+
tWR=self.ns(14),
86+
tWTR=2,
87+
tREFI=self.ns(64*1000*1000/4096, False),
88+
tRFC=self.ns(66),
89+
req_queue_size=8,
90+
read_time=32,
91+
write_time=16
92+
)
93+
self.submodules.sdrphy = gensdrphy.GENSDRPHY(platform.request("sdram"))
94+
self.register_sdram_phy(self.sdrphy, sdram_geom, sdram_timing)
9495

9596
self.submodules.spiflash = spiflash.SpiFlash(platform.request("spiflash2x"), dummy=4, div=6)
9697
self.flash_boot_address = 0x70000

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