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base repository: m-labs/misoc
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  • 3 commits
  • 6 files changed
  • 1 contributor

Commits on Mar 6, 2015

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Showing with 64 additions and 12 deletions.
  1. +17 −0 misoclib/com/liteeth/phy/__init__.py
  2. +12 −0 misoclib/com/uart/phy/__init__.py
  3. +2 −6 misoclib/soc/__init__.py
  4. +2 −2 targets/kc705.py
  5. +2 −2 targets/mlabs_video.py
  6. +29 −2 targets/simple.py
17 changes: 17 additions & 0 deletions misoclib/com/liteeth/phy/__init__.py
Original file line number Diff line number Diff line change
@@ -0,0 +1,17 @@
from misoclib.com.liteeth.common import *
from misoclib.com.liteeth.generic import *

from misoclib.com.liteeth.phy.sim import LiteEthPHYSim
from misoclib.com.liteeth.phy.mii import LiteEthPHYMII
from misoclib.com.liteeth.phy.gmii import LiteEthPHYGMII

def LiteEthPHY(clock_pads, pads, **kwargs):
# Autodetect PHY
if hasattr(pads, "source_stb"):
return LiteEthPHYSim(pads)
elif hasattr(clock_pads, "gtx") and flen(pads.tx_data) == 8:
return LiteEthPHYGMII(clock_pads, pads, **kwargs)
elif flen(pads.tx_data) == 4:
return LiteEthPHYMII(clock_pads, pads, **kwargs)
else:
raise ValueError("Unable to autodetect PHY from platform file, use direct instanciation")
12 changes: 12 additions & 0 deletions misoclib/com/uart/phy/__init__.py
Original file line number Diff line number Diff line change
@@ -0,0 +1,12 @@
from misoclib.com.liteeth.common import *
from misoclib.com.liteeth.generic import *

from misoclib.com.uart.phy.sim import UARTPHYSim
from misoclib.com.uart.phy.serial import UARTPHYSerial

def UARTPHY(pads, *args, **kwargs):
# Autodetect PHY
if hasattr(pads, "source_stb"):
return UARTPHYSim(pads, *args, **kwargs)
else:
return UARTPHYSerial(pads, *args, **kwargs)
8 changes: 2 additions & 6 deletions misoclib/soc/__init__.py
Original file line number Diff line number Diff line change
@@ -6,8 +6,7 @@
from migen.bank import csrgen
from migen.bus import wishbone, csr, wishbone2csr

from misoclib.com.uart.phy.serial import UARTPHYSerial
from misoclib.com.uart.phy.sim import UARTPHYSim
from misoclib.com.uart.phy import UARTPHY
from misoclib.com import uart
from misoclib.cpu import CPU, lm32, mor1kx
from misoclib.cpu.peripherals import identifier, timer
@@ -111,10 +110,7 @@ def __init__(self, platform, clk_freq, cpu_or_bridge=None,
self.register_mem("csr", self.mem_map["csr"], self.wishbone2csr.wishbone)

if with_uart:
if getattr(platform, "is_sim", False):
self.submodules.uart_phy = UARTPHYSim(platform.request("serial"))
else:
self.submodules.uart_phy = UARTPHYSerial(platform.request("serial"), clk_freq, uart_baudrate)
self.submodules.uart_phy = UARTPHY(platform.request("serial"), clk_freq, uart_baudrate)
self.submodules.uart = uart.UART(self.uart_phy)

if with_identifier:
4 changes: 2 additions & 2 deletions targets/kc705.py
Original file line number Diff line number Diff line change
@@ -7,7 +7,7 @@
from misoclib.soc import mem_decoder
from misoclib.soc.sdram import SDRAMSoC

from misoclib.com.liteeth.phy.gmii import LiteEthPHYGMII
from misoclib.com.liteeth.phy import LiteEthPHY
from misoclib.com.liteeth.mac import LiteEthMAC

class _CRG(Module):
@@ -133,7 +133,7 @@ class MiniSoC(BaseSoC):
def __init__(self, platform, **kwargs):
BaseSoC.__init__(self, platform, **kwargs)

self.submodules.ethphy = LiteEthPHYGMII(platform.request("eth_clocks"), platform.request("eth"))
self.submodules.ethphy = LiteEthPHY(platform.request("eth_clocks"), platform.request("eth"))
self.submodules.ethmac = LiteEthMAC(phy=self.ethphy, dw=32, interface="wishbone")
self.add_wb_slave(mem_decoder(self.mem_map["ethmac"]), self.ethmac.bus)
self.add_memory_region("ethmac", self.mem_map["ethmac"]+0x80000000, 0x2000)
4 changes: 2 additions & 2 deletions targets/mlabs_video.py
Original file line number Diff line number Diff line change
@@ -13,7 +13,7 @@
from misoclib.soc import mem_decoder
from misoclib.soc.sdram import SDRAMSoC

from misoclib.com.liteeth.phy.mii import LiteEthPHYMII
from misoclib.com.liteeth.phy import LiteEthPHY
from misoclib.com.liteeth.mac import LiteEthMAC

class _MXClockPads:
@@ -111,7 +111,7 @@ def __init__(self, platform, **kwargs):
self.submodules.buttons = gpio.GPIOIn(Cat(platform.request("user_btn", 0), platform.request("user_btn", 2)))
self.submodules.leds = gpio.GPIOOut(Cat(platform.request("user_led", i) for i in range(2)))

self.submodules.ethphy = LiteEthPHYMII(platform.request("eth_clocks"), platform.request("eth"))
self.submodules.ethphy = LiteEthPHY(platform.request("eth_clocks"), platform.request("eth"))
self.submodules.ethmac = LiteEthMAC(phy=self.ethphy, dw=32, interface="wishbone")
self.add_wb_slave(mem_decoder(self.mem_map["ethmac"]), self.ethmac.bus)
self.add_memory_region("ethmac", self.mem_map["ethmac"]+0x80000000, 0x2000)
31 changes: 29 additions & 2 deletions targets/simple.py
Original file line number Diff line number Diff line change
@@ -2,6 +2,8 @@
from migen.bus import wishbone

from misoclib.soc import SoC, mem_decoder
from misoclib.com.liteeth.phy import LiteEthPHY
from misoclib.com.liteeth.mac import LiteEthMAC

class _CRG(Module):
def __init__(self, clk_in):
@@ -17,7 +19,7 @@ def __init__(self, clk_in):
self.cd_sys.rst.eq(~rst_n)
]

class SimpleSoC(SoC):
class BaseSoC(SoC):
def __init__(self, platform, **kwargs):
SoC.__init__(self, platform,
clk_freq=int((1/(platform.default_clk_period))*1000000000),
@@ -27,4 +29,29 @@ def __init__(self, platform, **kwargs):
clk_in = platform.request(platform.default_clk_name)
self.submodules.crg = _CRG(clk_in if not hasattr(clk_in, "p") else clk_in.p)

default_subtarget = SimpleSoC
class MiniSoC(BaseSoC):
csr_map = {
"ethphy": 20,
"ethmac": 21
}
csr_map.update(BaseSoC.csr_map)

interrupt_map = {
"ethmac": 2,
}
interrupt_map.update(BaseSoC.interrupt_map)

mem_map = {
"ethmac": 0x30000000, # (shadow @0xb0000000)
}
mem_map.update(BaseSoC.mem_map)

def __init__(self, platform, **kwargs):
BaseSoC.__init__(self, platform, **kwargs)

self.submodules.ethphy = LiteEthPHY(platform.request("eth_clocks"), platform.request("eth"))
self.submodules.ethmac = LiteEthMAC(phy=self.ethphy, dw=32, interface="wishbone", with_hw_preamble_crc=False)
self.add_wb_slave(mem_decoder(self.mem_map["ethmac"]), self.ethmac.bus)
self.add_memory_region("ethmac", self.mem_map["ethmac"]+0x80000000, 0x2000)

default_subtarget = BaseSoC