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)
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]
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- def Platform (* args , toolchain = "vivado" , ** kwargs ):
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+ def Platform (* args , toolchain = "vivado" , programmer = "xc3sprog" , ** kwargs ):
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if toolchain == "ise" :
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xilinx_platform = XilinxISEPlatform
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elif toolchain == "vivado" :
@@ -396,7 +396,12 @@ def __init__(self, crg_factory=lambda p: CRG_DS(p, "clk156", "cpu_reset")):
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xilinx_platform .__init__ (self , "xc7k325t-ffg900-2" , _io , crg_factory , _connectors )
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def create_programmer (self ):
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- return XC3SProg ("jtaghs1_fast" , "bscan_spi_kc705.bit" )
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+ if programmer == "xc3sprog" :
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+ return XC3SProg ("jtaghs1_fast" , "bscan_spi_kc705.bit" )
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+ elif programmer == "vivado" :
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+ return VivadoProgrammer ()
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+ else :
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+ raise ValueError ("{} programmer is not supported" .format (programmer ))
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def do_finalize (self , fragment ):
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try :
@@ -415,4 +420,5 @@ def do_finalize(self, fragment):
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self .add_platform_command ("CONFIG DCI_CASCADE = \" 33 32 34\" ;" )
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else :
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self .add_platform_command ("set_property DCI_CASCADE {{32 34}} [get_iobanks 33]" )
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+
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return RealPlatform (* args , ** kwargs )
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