m-labs · Feb 28, 2015 · Feb 28, 2015 · Feb 28, 2015 · Feb 28, 2015 · Feb 28, 2015
diff --git a/misoclib/com/liteeth/README b/misoclib/com/liteeth/README
@@ -3,23 +3,22 @@
               / /__/ / __/ -_) _// __/ _ \
              /____/_/\__/\__/___/\__/_//_/
 
-           Copyright 2012-2015 / EnjoyDigital
-                florent@enjoy-digital.fr
+        Copyright 2012-2015 / EnjoyDigital / M-Labs Ltd
 
        A small footprint and configurable Ethernet core
          with UDP/IP hw stack and Etherbone frontend
                   powered by Migen
 
 [> Doc
 ---------
-HTML : www.enjoy-digital.fr/litex/liteeth/
-PDF  : www.enjoy-digital.fr/litex/liteeth.pdf
+HTML : www.enjoy-digital.fr/liteeth/
+PDF  : www.enjoy-digital.fr/liteeth.pdf
 
 [> Intro
 ---------
 LiteEth provides a small footprint and configurable Ethernet core.
 
-LiteEth is part of LiteX libraries whose aims are to lower entry level of
+LiteEth is part of MiSoC libraries whose aims are to lower entry level of
 complex FPGA cores by providing simple, elegant and efficient implementations
 ofcomponents used in today's SoC such as Ethernet, SATA, PCIe, SDRAM Controller...
 
@@ -33,9 +32,8 @@ LiteEth uses technologies developed in partnership with M-Labs Ltd:
  - Migen enables generating HDL with Python in an efficient way.
  - MiSoC provides the basic blocks to build a powerful and small footprint SoC.
 
-LiteEth can be used as a Migen/MiSoC library (by simply installing  it
-with the provided setup.py) or can be integrated with your standard design flow
-by generating the verilog rtl that you will use as a standard core.
+LiteEth can be used as MiSoC library or can be integrated with your standard
+design flow by generating the verilog rtl that you will use as a standard core.
 
 [> Features
 -----------
@@ -64,53 +62,41 @@ devel [AT] lists.m-labs.hk.
   python3 setup.py install
   cd ..
 
-Note: in case you have issues with Migen, please retry
-with our fork at:
-  https://github.com/enjoy-digital/misoc
-until new features are merged.
+3. Obtain MiSoC:
+  git clone https://github.com/m-labs/misoc --recursive
 
-3. Obtain LiteScope and install it:
-  git clone https://github.com/enjoy-digital/litescope
-  cd litescope
-  python3 setup.py install
-  cd ..
-
-4. Obtain LiteEth
-  git clone https://github.com/enjoy-digital/liteeth
-
-5. Build and load UDP loopback design (only for KC705 for now):
-  python3 make.py -t udp all
+4. Build and load UDP loopback design (only for KC705 for now):
+  go to misoclib/com/liteeth/example_designs/
+  run ./make.py -t udp all load-bitstream
 
-6. Test design (only for KC705 for now):
+5. Test design (only for KC705 for now):
   try to ping 192.168.1.40
-  go to ./test directory:
-  change com port in config.py to your com port
-  run make test_udp
+  go to [..]/example_designs/test/
+  run ./make.py udp
 
-7. Build and load Etherbone design (only for KC705 for now):
-  python3 make.py -t etherbone all
+6. Build and load Etherbone design (only for KC705 for now):
+  python3 make.py -t etherbone all load-bitstream
 
-8. Test design (only for KC705 for now):
+7. Test design (only for KC705 for now):
   try to ping 192.168.1.40
-  go to ./test directory run:
-  run make test_etherbone
+  go to [..]/example_designs/test/
+  run ./make.py etherbone
 
 [> Simulations:
-  Simulations are available in ./liteth/test/:
+  Simulations are available in misoclib/com/liteeth/test/:
     - mac_core_tb
     - mac_wishbone_tb
     - arp_tb
     - ip_tb
     - icmp_tb
     - udp_tb
-  All ethernet layers have their own model tested against real Ethernet dumps (dumps.py)
-  To run a simulation, move to ./liteeth/test and run:
+  All ethernet layers have their own model tested against real ethernet dumps (dumps.py)
+  To run a simulation, move to misoclib/com/liteeth/test/ and run:
     make simulation_name
 
 [> Tests :
-  An UDP loopback example is provided and be controlled with: ./test/test_udp.py
-  An Etherbone example with Wishbone SRAM is provided and can be controlled with:
-  ./test/test_etherbone.py
+  An Etherbone example with Wishbone SRAM and an UDP loopback example are provided.
+  Please goto to Getting Started section to see how to run the tests.
 
 [> License
 -----------
@@ -129,7 +115,7 @@ do them if possible:
 --------------------------
 We love open-source hardware and like sharing our designs with others.
 
-LiteEth is developed and maintained by EnjoyDigital.
+LiteEth is mainly developed and maintained by EnjoyDigital.
 
 If you would like to know more about LiteEth or if you are already a happy
 user and would like to extend it for your needs, EnjoyDigital can provide standard

diff --git a/misoclib/com/liteeth/doc/source/docs/getting_started/downloads.rst b/misoclib/com/liteeth/doc/source/docs/getting_started/downloads.rst
@@ -3,41 +3,6 @@
 ====================
 Download and install
 ====================
-1. Install Python3 and your vendor's software
+Please follow Getting started section of LiteEth README_.
 
-2. Obtain Migen and install it:
-  - git clone https://github.com/m-labs/migen
-  - cd migen
-  - python3 setup.py install
-  - cd ..
-
-.. note::
-  In case you have issues with Migen, please retry with our forks at:
-  https://github.com/enjoy-digital/migen
-  until new features are merged.
-
-3. Obtain LiteScope and install it:
-  - git clone https://github.com/enjoy-digital/litescope
-  - cd litescope
-  - python3 setup.py install
-  - cd ..
-
-4. Obtain LiteEth
-  - git clone https://github.com/enjoy-digital/liteeth
-
-5. Build and load UDP loopback design (only for KC705 for now):
-  - python3 make.py -t udp all
-
-6. Test design (only for KC705 for now):
-  - try to ping 192.168.1.40
-  - go to ./test directory:
-  - change com port in config.py to your com port
-  - run make test_udp
-
-7. Build and load Etherbone design (only for KC705 for now):
-  - python3 make.py -t etherbone all
-
-8. Test design (only for KC705 for now):
-  - try to ping 192.168.1.40
-  - go to ./test directory run:
-  - run make test_etherbone
+.. _README: https://github.com/m-labs/misoc/blob/master/misoclib/com/liteeth/README
diff --git a/misoclib/com/liteeth/doc/source/docs/intro/about.rst b/misoclib/com/liteeth/doc/source/docs/intro/about.rst
@@ -6,7 +6,7 @@ About LiteEth
 
 LiteEth provides a small footprint and configurable Ethernet core.
 
-LiteEth is part of LiteX libraries whose aims are to lower entry level of
+LiteEth is part of MiSoC libraries whose aims are to lower entry level of
 complex FPGA cores by providing simple, elegant and efficient implementations
 ofcomponents used in today's SoC such as Ethernet, SATA, PCIe, SDRAM Controller...
 
@@ -20,9 +20,8 @@ LiteEth uses technologies developed in partnership with M-Labs Ltd:
  - Migen enables generating HDL with Python in an efficient way.
  - MiSoC provides the basic blocks to build a powerful and small footprint SoC.
 
-LiteEth can be used as a Migen/MiSoC library (by simply installing  it
-with the provided setup.py) or can be integrated with your standard design flow
-by generating the verilog rtl that you will use as a standard core.
+LiteEth can be used as MiSoC library or can be integrated with your standard
+design flow by generating the verilog rtl that you will use as a standard core.
 
 .. _about-toolchain:
 
@@ -43,7 +42,7 @@ Support and Consulting
 ======================
 We love open-source hardware and like sharing our designs with others.
 
-LiteEth is developed and maintained by EnjoyDigital.
+LiteEth is mainly developed and maintained by EnjoyDigital.
 
 If you would like to know more about LiteEth or if you are already a happy user
 and would like to extend it for your needs, EnjoyDigital can provide standard

diff --git a/misoclib/com/liteeth/example_designs/make.py b/misoclib/com/liteeth/example_designs/make.py
@@ -10,19 +10,9 @@
 from mibuild import tools
 from mibuild.xilinx.common import *
 
-sys.path.append("../../../../") # Temporary
+from misoclib.soc import cpuif
 from misoclib.com.liteeth.common import *
 
-def get_csr_csv(regions):
-	r = ""
-	for name, origin, busword, obj in regions:
-		if not isinstance(obj, Memory):
-			for csr in obj:
-				nr = (csr.size + busword - 1)//busword
-				r += "{}_{},0x{:08x},{},{}\n".format(name, csr.name, origin, nr, "ro" if isinstance(csr, CSRStatus) else "rw")
-				origin += 4*nr
-	return r
-
 def _import(default, name):
 	return importlib.import_module(default + "." + name)
 
@@ -61,17 +51,20 @@ def _get_args():
 	args = _get_args()
 
 	# create top-level Core object
-	target_module = _import("misoclib.com.liteeth.example_designs.targets", args.target)
+	target_module = _import("targets", args.target)
 	if args.sub_target:
 		top_class = getattr(target_module, args.sub_target)
 	else:
 		top_class = target_module.default_subtarget
 
 	if args.platform is None:
-		platform_name = top_class.default_platform
+		if hasattr(top_class, "default_platform"):
+			platform_name = top_class.default_platform
+		else:
+			raise ValueError("Target has no default platform, specify a platform with -p your_platform")
 	else:
 		platform_name = args.platform
-	platform_module = _import("misoclib.com.liteeth.example_designs.platforms", platform_name)
+	platform_module = _import("mibuild.platforms", platform_name)
 	platform_kwargs = dict((k, autotype(v)) for k, v in args.platform_option)
 	platform = platform_module.Platform(**platform_kwargs)
 
@@ -128,7 +121,7 @@ def _get_args():
 		subprocess.call(["rm", "-rf", "build/*"])
 
 	if actions["build-csr-csv"]:
-		csr_csv = get_csr_csv(soc.cpu_csr_regions)
+		csr_csv = cpuif.get_csr_csv(soc.csr_regions)
 		write_to_file(args.csr_csv, csr_csv)
 
 	if actions["build-bitstream"]:

diff --git a/misoclib/com/liteeth/example_designs/platforms/kc705.py b/misoclib/com/liteeth/example_designs/platforms/kc705.py