@@ -27,14 +27,15 @@ class SoC(Module):
2727 "timer0" : 1 ,
2828 }
2929 mem_map = {
30+ "rom" : 0x00000000 , # (shadow @0x80000000)
3031 "sram" : 0x10000000 , # (shadow @0x90000000)
3132 "sdram" : 0x40000000 , # (shadow @0xc0000000)
3233 "csr" : 0x60000000 , # (shadow @0xe0000000)
3334 }
3435 def __init__ (self , platform , clk_freq , cpu_or_bridge = None ,
3536 with_cpu = True , cpu_type = "lm32" , cpu_reset_address = 0x00000000 ,
3637 cpu_boot_file = "software/bios/bios.bin" ,
37- with_rom = False , rom_size = 0xa000 ,
38+ with_rom = False , rom_size = 0x8000 ,
3839 with_sram = True , sram_size = 4096 ,
3940 with_sdram = False , sdram_size = 64 * 1024 ,
4041 with_csr = True , csr_data_width = 8 , csr_address_width = 14 ,
@@ -86,7 +87,7 @@ def __init__(self, platform, clk_freq, cpu_or_bridge=None,
8687
8788 if with_rom :
8889 self .submodules .rom = wishbone .SRAM (rom_size , read_only = True )
89- self .register_mem ( "rom" , self . cpu_reset_address , self .rom .bus , rom_size )
90+ self .register_rom ( self .rom .bus , rom_size )
9091
9192 if with_sram :
9293 self .submodules .sram = wishbone .SRAM (sram_size )
@@ -140,9 +141,9 @@ def register_mem(self, name, address, interface, size=None):
140141 if size is not None :
141142 self .add_memory_region (name , address , size )
142143
143- # XXX for retro-compatibilty, we should maybe use directly register_mem in targets
144- def register_rom ( self , interface ):
145- self .register_mem ("rom" , self .cpu_reset_address , interface , size = self . rom_size )
144+ def register_rom ( self , interface , rom_size = 0xa000 ):
145+ self . add_wb_slave ( mem_decoder ( self . mem_map [ "rom" ]) , interface )
146+ self .add_memory_region ("rom" , self .cpu_reset_address , rom_size )
146147
147148 def check_csr_region (self , name , origin ):
148149 for n , o , l , obj in self .csr_regions :
0 commit comments