soc: add_cpu_csr_region -> add_csr_region

Joe Britton · Joe Britton · commit 0127de9bb59f · 2015-02-27T15:02:28.000-07:00
diff --git a/soc/targets/artiq_kc705.py b/soc/targets/artiq_kc705.py
@@ -103,7 +103,7 @@ def __init__(self, platform, cpu_type="or1k", with_test_gen=False,
         rtio_csrs = self.rtio.get_csrs()
         self.submodules.rtiowb = wbgen.Bank(rtio_csrs)
         self.add_wb_slave(lambda a: a[26:29] == 2, self.rtiowb.bus)
-        self.add_cpu_csr_region("rtio", 0xa0000000, 32, rtio_csrs)
+        self.add_csr_region("rtio", 0xa0000000, 32, rtio_csrs)
 
         dds_pads = platform.request("dds")
         self.submodules.dds = ad9858.AD9858(dds_pads)
diff --git a/soc/targets/artiq_ppro.py b/soc/targets/artiq_ppro.py
@@ -122,7 +122,7 @@ def __init__(self, platform, cpu_type="or1k", ramcon_type="minicon",
         rtio_csrs = self.rtio.get_csrs()
         self.submodules.rtiowb = wbgen.Bank(rtio_csrs)
         self.add_wb_slave(lambda a: a[26:29] == 2, self.rtiowb.bus)
-        self.add_cpu_csr_region("rtio", 0xa0000000, 32, rtio_csrs)
+        self.add_csr_region("rtio", 0xa0000000, 32, rtio_csrs)
 
         if with_test_gen:
             self.submodules.test_gen = _TestGen(platform.request("ttl", 8))
