Skip to content

Commit

Permalink
soc: add_cpu_csr_region -> add_csr_region
Browse files Browse the repository at this point in the history
Joe Britton committed Feb 27, 2015
1 parent f307897 commit 0127de9
Showing 2 changed files with 2 additions and 2 deletions.
2 changes: 1 addition & 1 deletion soc/targets/artiq_kc705.py
Original file line number Diff line number Diff line change
@@ -103,7 +103,7 @@ def __init__(self, platform, cpu_type="or1k", with_test_gen=False,
rtio_csrs = self.rtio.get_csrs()
self.submodules.rtiowb = wbgen.Bank(rtio_csrs)
self.add_wb_slave(lambda a: a[26:29] == 2, self.rtiowb.bus)
self.add_cpu_csr_region("rtio", 0xa0000000, 32, rtio_csrs)
self.add_csr_region("rtio", 0xa0000000, 32, rtio_csrs)

dds_pads = platform.request("dds")
self.submodules.dds = ad9858.AD9858(dds_pads)
2 changes: 1 addition & 1 deletion soc/targets/artiq_ppro.py
Original file line number Diff line number Diff line change
@@ -122,7 +122,7 @@ def __init__(self, platform, cpu_type="or1k", ramcon_type="minicon",
rtio_csrs = self.rtio.get_csrs()
self.submodules.rtiowb = wbgen.Bank(rtio_csrs)
self.add_wb_slave(lambda a: a[26:29] == 2, self.rtiowb.bus)
self.add_cpu_csr_region("rtio", 0xa0000000, 32, rtio_csrs)
self.add_csr_region("rtio", 0xa0000000, 32, rtio_csrs)

if with_test_gen:
self.submodules.test_gen = _TestGen(platform.request("ttl", 8))

0 comments on commit 0127de9

Please sign in to comment.