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enjoy-digitalenjoy-digital
committedMar 1, 2015
mibuild: initial Verilator support
·
0.9.20.1
1 parent 8f81ae6 commit 382ca37

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‎mibuild/platforms/sim.py

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from mibuild.generic_platform import *
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from mibuild.crg import SimpleCRG
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from mibuild.sim.verilator import VerilatorPlatform
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class SimPins(Pins):
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def __init__(self, n):
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Pins.__init__(self, "s "*n)
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_io = [
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("sys_clk", 0, SimPins(1)),
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("sys_rst", 0, SimPins(1)),
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("serial", 0,
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Subsignal("source_stb", SimPins(1)),
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Subsignal("source_ack", SimPins(1)),
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Subsignal("source_data", SimPins(8)),
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Subsignal("sink_stb", SimPins(1)),
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Subsignal("sink_ack", SimPins(1)),
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Subsignal("sink_data", SimPins(8)),
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),
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]
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class Platform(VerilatorPlatform):
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is_sim = True
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default_clk_name = "sys_clk"
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default_clk_period = 1000 # on modern computers simulate at ~ 1MHz
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def __init__(self):
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VerilatorPlatform.__init__(self, "SIM", _io)
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def do_finalize(self, fragment):
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pass

‎mibuild/sim/__init__.py

Whitespace-only changes.

‎mibuild/sim/dut_tb.cpp

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// This file is Copyright (c) 2015 Florent Kermarrec <florent@enjoy-digital.fr>
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// License: BSD
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#include <time.h>
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#include "Vdut.h"
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#include "verilated.h"
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#include "verilated_vcd_c.h"
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#include <stdio.h>
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#include <stdlib.h>
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#include <string.h>
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#include <unistd.h>
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#include <sys/select.h>
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#include <sys/socket.h>
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#include <sys/ioctl.h>
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#include <sys/stat.h>
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#include <sys/types.h>
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#include <termios.h>
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int trace = 0;
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struct termios orig_termios;
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void reset_terminal_mode(void)
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{
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tcsetattr(0, TCSANOW, &orig_termios);
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}
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void set_conio_terminal_mode(void)
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{
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struct termios new_termios;
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/* take two copies - one for now, one for later */
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tcgetattr(0, &orig_termios);
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memcpy(&new_termios, &orig_termios, sizeof(new_termios));
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/* register cleanup handler, and set the new terminal mode */
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atexit(reset_terminal_mode);
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cfmakeraw(&new_termios);
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tcsetattr(0, TCSANOW, &new_termios);
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}
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int kbhit(void)
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{
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struct timeval tv = { 0L, 0L };
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fd_set fds;
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FD_ZERO(&fds);
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FD_SET(0, &fds);
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return select(1, &fds, NULL, NULL, &tv);
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}
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int getch(void)
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{
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int r;
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unsigned char c;
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if ((r = read(0, &c, sizeof(c))) < 0) {
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return r;
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} else {
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return c;
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}
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}
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vluint64_t main_time = 0;
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double sc_time_stamp () {
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return main_time;
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}
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Vdut* dut;
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VerilatedVcdC* tfp;
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unsigned int tick;
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/* ios */
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/* ios */
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int console_service() {
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/* fpga --> console */
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SERIAL_SOURCE_ACK = 1;
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if(SERIAL_SOURCE_STB == 1) {
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if (SERIAL_SOURCE_DATA == '\n')
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putchar('\r');
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putchar(SERIAL_SOURCE_DATA);
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fflush(stdout);
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}
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/* console --> fpga */
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SERIAL_SINK_STB = 0;
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if (tick%(1000) == 0) {
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if(kbhit()) {
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char c = getch();
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if (c == 27 && !kbhit()) {
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printf("\r\n");
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return -1;
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} else {
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SERIAL_SINK_STB = 1;
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SERIAL_SINK_DATA = c;
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}
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}
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}
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return 0;
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}
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void sim_tick() {
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SYS_CLK = tick%2;
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dut->eval();
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if (trace)
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tfp->dump(tick);
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tick++;
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}
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void sim_init() {
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int i;
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tick = 0;
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#ifdef SYS_RST
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SYS_RST = 1;
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SYS_CLK = 0;
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for (i=0; i<8; i++)
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sim_tick();
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SYS_RST = 0;
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#endif
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}
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int main(int argc, char **argv, char **env) {
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clock_t start;
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clock_t end;
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float speed;
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set_conio_terminal_mode();
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Verilated::commandArgs(argc, argv);
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dut = new Vdut;
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Verilated::traceEverOn(true);
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tfp = new VerilatedVcdC;
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dut->trace(tfp, 99);
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tfp->open("dut.vcd");
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start = clock();
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sim_init();
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bool run = true;
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while(run) {
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sim_tick();
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if (SYS_CLK) {
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if (console_service() != 0)
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run = false;
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}
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}
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end = clock();
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speed = (tick/2)/((end-start)/CLOCKS_PER_SEC);
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printf("averate speed: %3.3f MHz\n\r", speed/1000000);
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tfp->close();
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exit(0);
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}

‎mibuild/sim/verilator.py

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# This file is Copyright (c) 2015 Florent Kermarrec <florent@enjoy-digital.fr>
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# License: BSD
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import os, subprocess
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from migen.fhdl.std import *
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from migen.fhdl.structure import _Fragment
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from mibuild.generic_platform import *
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def _build_tb(platform, template):
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def io_name(ressource, subsignal=None):
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res = platform.lookup_request(ressource)
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if subsignal is not None:
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res = getattr(res, subsignal)
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return platform.vns.get_name(res)
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ios = """
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#define SYS_CLK dut->{sys_clk}
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#define SERIAL_SOURCE_STB dut->{serial_source_stb}
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#define SERIAL_SOURCE_ACK dut->{serial_source_ack}
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#define SERIAL_SOURCE_DATA dut->{serial_source_data}
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#define SERIAL_SINK_STB dut->{serial_sink_stb}
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#define SERIAL_SINK_ACK dut->{serial_sink_ack}
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#define SERIAL_SINK_DATA dut->{serial_sink_data}
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""".format(
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sys_clk=io_name("sys_clk"),
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serial_source_stb=io_name("serial", "source_stb"),
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serial_source_ack=io_name("serial", "source_ack"),
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serial_source_data=io_name("serial", "source_data"),
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serial_sink_stb=io_name("serial", "sink_stb"),
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serial_sink_ack=io_name("serial", "sink_ack"),
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serial_sink_data=io_name("serial", "sink_data"),
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)
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content = ""
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f = open(template, "r")
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done = False
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for l in f:
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content += l
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if "/* ios */" in l and not done:
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content += ios
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done = True
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f.close()
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tools.write_to_file("dut_tb.cpp", content)
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def _build_sim(platform, build_name, include_paths, verilator_root_path, template_file, trace):
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include = ""
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for path in include_paths:
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include += "-I"+path+" "
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build_script_contents = """# Autogenerated by mibuild
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rm -rf obj_dir/
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verilator {disable_warnings} -O3 --cc dut.v --exe dut_tb.cpp {trace} {include}
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make -j -C obj_dir/ -f Vdut.mk Vdut VERILATOR_ROOT={verilator_root}
Has conversations. Original line has conversations.
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""".format(verilator_root= os.path.join("../../", verilator_root_path), # XXX
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disable_warnings="-Wno-lint -Wno-INITIALDLY",
Has conversations. Original line has conversations.
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trace="-trace" if trace else "",
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include=include)
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build_script_file = "build_" + build_name + ".sh"
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tools.write_to_file(build_script_file, build_script_contents, force_unix=True)
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_build_tb(platform, os.path.join("../", template_file)) # XXX
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r = subprocess.call(["bash", build_script_file])
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if r != 0:
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raise OSError("Subprocess failed")
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def _run_sim(build_name):
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run_script_contents = """obj_dir/Vdut
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"""
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run_script_file = "run_" + build_name + ".sh"
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tools.write_to_file(run_script_file, run_script_contents, force_unix=True)
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r = subprocess.call(["bash", run_script_file])
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if r != 0:
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raise OSError("Subprocess failed")
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class VerilatorPlatform(GenericPlatform):
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# XXX fix template / verilator_path
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def build(self, soc, build_dir="build", build_name="top", run=True, trace=True,
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template_file="../migen/mibuild/sim/dut_tb.cpp",
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verilator_root_path="../verilator"):
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tools.mkdir_noerror(build_dir)
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os.chdir(build_dir)
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self.soc = soc
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fragment = soc.get_fragment()
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self.finalize(fragment)
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v_src, vns = self.get_verilog(fragment)
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named_sc, named_pc = self.resolve_signals(vns)
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self.vns = vns
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v_file = "dut.v"
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tools.write_to_file(v_file, v_src)
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include_paths = []
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for source in self.sources:
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path = os.path.dirname(source[0]).replace("\\", "\/")
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if path not in include_paths:
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include_paths.append(path)
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include_paths += self.verilog_include_paths
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_build_sim(self, build_name, include_paths, verilator_root_path, template_file, trace)
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if run:
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_run_sim(build_name)
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os.chdir("..")

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