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soc: add initial verilator sim support: ./make.py -t simple -p sim bu…
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…ild-bitstream :)
enjoy-digital committed Mar 1, 2015
1 parent 4f37d29 commit f58394f
Showing 3 changed files with 19 additions and 11 deletions.
16 changes: 8 additions & 8 deletions misoclib/com/uart/__init__.py
Original file line number Diff line number Diff line change
@@ -15,16 +15,16 @@ def __init__(self, phy):
###
self.sync += [
If(self._rxtx.re,
phy.tx.sink.stb.eq(1),
phy.tx.sink.data.eq(self._rxtx.r),
).Elif(phy.tx.sink.ack,
phy.tx.sink.stb.eq(0)
phy.sink.stb.eq(1),
phy.sink.data.eq(self._rxtx.r),
).Elif(phy.sink.ack,
phy.sink.stb.eq(0)
),
If(phy.rx.source.stb,
self._rxtx.w.eq(phy.rx.source.data)
If(phy.source.stb,
self._rxtx.w.eq(phy.source.data)
)
]
self.comb += [
self.ev.tx.trigger.eq(phy.tx.sink.stb & phy.tx.sink.ack),
self.ev.rx.trigger.eq(phy.rx.source.stb) #phy.rx.source.ack supposed to be always 1
self.ev.tx.trigger.eq(phy.sink.stb & phy.sink.ack),
self.ev.rx.trigger.eq(phy.source.stb) #phy.source.ack supposed to be always 1
]
2 changes: 0 additions & 2 deletions misoclib/com/uart/phy/sim.py
Original file line number Diff line number Diff line change
@@ -3,8 +3,6 @@

class UARTPHYSim(Module):
def __init__(self, pads):
self.dw = 8
self.tuning_word = Signal(32)
self.sink = Sink([("data", 8)])
self.source = Source([("data", 8)])

12 changes: 11 additions & 1 deletion misoclib/soc/__init__.py
Original file line number Diff line number Diff line change
@@ -7,13 +7,20 @@
from migen.bus import wishbone, csr, wishbone2csr

from misoclib.com.uart.phy.serial import UARTPHYSerial
from misoclib.com.uart.phy.sim import UARTPHYSim
from misoclib.com import uart
from misoclib.cpu import CPU, lm32, mor1kx
from misoclib.cpu.peripherals import identifier, timer

def mem_decoder(address, start=26, end=29):
return lambda a: a[start:end] == ((address >> (start+2)) & (2**(end-start))-1)

def is_sim(platform):
if hasattr(platform, "is_sim"):

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@sbourdeauducq

sbourdeauducq Mar 3, 2015

Member

getattr(platform, "is_sim", False). Guess you can remove the function after this.

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@enjoy-digital

enjoy-digital Mar 3, 2015

Author Contributor

thanks!

return platform.is_sim
else:
return False

class SoC(Module):
csr_map = {
"crg": 0, # user
@@ -107,7 +114,10 @@ def __init__(self, platform, clk_freq, cpu_or_bridge=None,
self.register_mem("csr", self.mem_map["csr"], self.wishbone2csr.wishbone)

if with_uart:
self.submodules.uart_phy = UARTPHYSerial(platform.request("serial"), clk_freq, uart_baudrate)
if is_sim(platform):
self.submodules.uart_phy = UARTPHYSim(platform.request("serial"))
else:
self.submodules.uart_phy = UARTPHYSerial(platform.request("serial"), clk_freq, uart_baudrate)
self.submodules.uart = uart.UART(self.uart_phy)

if with_identifier:

1 comment on commit f58394f

@sbourdeauducq
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Yay!

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