gensoc: cpus now directly add their verilog sources

enjoy-digital · enjoy-digital · commit 09fbbca53e74 · 2015-02-26T20:49:21.000+01:00
diff --git a/misoclib/gensoc/__init__.py b/misoclib/gensoc/__init__.py
@@ -1,4 +1,3 @@
-import os
 from operator import itemgetter
 from math import ceil
 
@@ -48,9 +47,9 @@ def __init__(self, platform, clk_freq, cpu_reset_address, sram_size=4096, l2_siz
 
 		# Wishbone
 		if cpu_type == "lm32":
-			self.submodules.cpu = lm32.LM32(cpu_reset_address)
+			self.submodules.cpu = lm32.LM32(platform, cpu_reset_address)
 		elif cpu_type == "or1k":
-			self.submodules.cpu = mor1kx.MOR1KX(cpu_reset_address)
+			self.submodules.cpu = mor1kx.MOR1KX(platform, cpu_reset_address)
 		else:
 			raise ValueError("Unsupported CPU type: "+cpu_type)
 		self.submodules.sram = wishbone.SRAM(sram_size)
@@ -74,18 +73,6 @@ def __init__(self, platform, clk_freq, cpu_reset_address, sram_size=4096, l2_siz
 			log2_int(l2_size) if l2_size else 0)
 		self.submodules.timer0 = timer.Timer()
 
-		# add CPU Verilog sources
-		if cpu_type == "lm32":
-			platform.add_sources(os.path.join("extcores", "lm32", "submodule", "rtl"),
-				"lm32_cpu.v", "lm32_instruction_unit.v", "lm32_decoder.v",
-				"lm32_load_store_unit.v", "lm32_adder.v", "lm32_addsub.v", "lm32_logic_op.v",
-				"lm32_shifter.v", "lm32_multiplier.v", "lm32_mc_arithmetic.v",
-				"lm32_interrupt.v", "lm32_ram.v", "lm32_dp_ram.v", "lm32_icache.v",
-				"lm32_dcache.v", "lm32_debug.v", "lm32_itlb.v", "lm32_dtlb.v")
-			platform.add_verilog_include_path(os.path.join("extcores", "lm32"))
-		if cpu_type == "or1k":
-			platform.add_source_dir(os.path.join("extcores", "mor1kx", "submodule", "rtl", "verilog"))
-
 	def register_rom(self, rom_wb_if, bios_size=0xa000):
 		if self._rom_registered:
 			raise FinalizeError
diff --git a/misoclib/lm32/__init__.py b/misoclib/lm32/__init__.py
@@ -1,8 +1,10 @@
+import os
+
 from migen.fhdl.std import *
 from migen.bus import wishbone
 
 class LM32(Module):
-	def __init__(self, eba_reset):
+	def __init__(self, platform, eba_reset):
 		self.ibus = i = wishbone.Interface()
 		self.dbus = d = wishbone.Interface()
 		self.interrupt = Signal(32)
@@ -49,3 +51,12 @@ def __init__(self, eba_reset):
 			self.ibus.adr.eq(i_adr_o[2:]),
 			self.dbus.adr.eq(d_adr_o[2:])
 		]
+
+		# add Verilog sources
+		platform.add_sources(os.path.join("extcores", "lm32", "submodule", "rtl"),
+				"lm32_cpu.v", "lm32_instruction_unit.v", "lm32_decoder.v",
+				"lm32_load_store_unit.v", "lm32_adder.v", "lm32_addsub.v", "lm32_logic_op.v",
+				"lm32_shifter.v", "lm32_multiplier.v", "lm32_mc_arithmetic.v",
+				"lm32_interrupt.v", "lm32_ram.v", "lm32_dp_ram.v", "lm32_icache.v",
+				"lm32_dcache.v", "lm32_debug.v", "lm32_itlb.v", "lm32_dtlb.v")
+		platform.add_verilog_include_path(os.path.join("extcores", "lm32"))
diff --git a/misoclib/mor1kx/__init__.py b/misoclib/mor1kx/__init__.py
@@ -1,8 +1,10 @@
+import os
+
 from migen.fhdl.std import *
 from migen.bus import wishbone
 
 class MOR1KX(Module):
-	def __init__(self, reset_pc):
+	def __init__(self, platform, reset_pc):
 		self.ibus = i = wishbone.Interface()
 		self.dbus = d = wishbone.Interface()
 		self.interrupt = Signal(32)
@@ -71,3 +73,6 @@ def __init__(self, reset_pc):
 			self.ibus.adr.eq(i_adr_o[2:]),
 			self.dbus.adr.eq(d_adr_o[2:])
 		]
+
+		# add Verilog sources
+		platform.add_source_dir(os.path.join("extcores", "mor1kx", "submodule", "rtl", "verilog"))
