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enjoy-digitalenjoy-digital
committedMar 3, 2015
sdram: pass phy_settings to LASMIcon, MiniCON and init_sequence
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0.120.1
1 parent 2f7206b commit 9210272

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6 files changed

+52
-52
lines changed

6 files changed

+52
-52
lines changed
 

Diff for: ‎make.py

+1-1
Original file line numberDiff line numberDiff line change
@@ -156,7 +156,7 @@ def _get_args():
156156

157157
for sdram_phy in ["sdrphy", "ddrphy"]:
158158
if hasattr(soc, sdram_phy):
159-
sdram_phy_header = initsequence.get_sdram_phy_header(getattr(soc, sdram_phy))
159+
sdram_phy_header = initsequence.get_sdram_phy_header(getattr(soc, sdram_phy).settings)
160160
write_to_file("software/include/generated/sdram_phy.h", boilerplate + sdram_phy_header)
161161
mem_header = cpuif.get_mem_header(soc.memory_regions, getattr(soc, "flash_boot_address", None))
162162
write_to_file("software/include/generated/mem.h", boilerplate + mem_header)

Diff for: ‎misoclib/mem/sdram/core/__init__.py

+2-2
Original file line numberDiff line numberDiff line change
@@ -15,14 +15,14 @@ def __init__(self, phy, ramcon_type, sdram_geom, sdram_timing, **kwargs):
1515

1616
# LASMICON
1717
if ramcon_type == "lasmicon":
18-
self.submodules.controller = controller = lasmicon.LASMIcon(phy, sdram_geom, sdram_timing, **kwargs)
18+
self.submodules.controller = controller = lasmicon.LASMIcon(phy.settings, sdram_geom, sdram_timing, **kwargs)
1919
self.comb += Record.connect(controller.dfi, self.dfii.slave)
2020

2121
self.submodules.crossbar = crossbar = Crossbar([controller.lasmic], controller.nrowbits)
2222

2323
# MINICON
2424
elif ramcon_type == "minicon":
25-
self.submodules.controller = controller = minicon.Minicon(phy, sdram_geom, sdram_timing)
25+
self.submodules.controller = controller = minicon.Minicon(phy.settings, sdram_geom, sdram_timing)
2626
self.comb += Record.connect(controller.dfi, self.dfii.slave)
2727
else:
2828
raise ValueError("Unsupported SDRAM controller type: {}".format(self.ramcon_type))

Diff for: ‎misoclib/mem/sdram/core/lasmicon/__init__.py

+11-11
Original file line numberDiff line numberDiff line change
@@ -6,24 +6,24 @@
66
from misoclib.mem.sdram.core.lasmicon.multiplexer import *
77

88
class LASMIcon(Module):
9-
def __init__(self, phy, geom_settings, timing_settings, **kwargs):
10-
if phy.settings.memtype in ["SDR"]:
11-
burst_length = phy.settings.nphases*1 # command multiplication*SDR
12-
elif phy.settings.memtype in ["DDR", "LPDDR", "DDR2", "DDR3"]:
13-
burst_length = phy.settings.nphases*2 # command multiplication*DDR
9+
def __init__(self, phy_settings, geom_settings, timing_settings, **kwargs):
10+
if phy_settings.memtype in ["SDR"]:
11+
burst_length = phy_settings.nphases*1 # command multiplication*SDR
12+
elif phy_settings.memtype in ["DDR", "LPDDR", "DDR2", "DDR3"]:
13+
burst_length = phy_settings.nphases*2 # command multiplication*DDR
1414
address_align = log2_int(burst_length)
1515

1616
self.dfi = dfi.Interface(geom_settings.mux_a,
1717
geom_settings.bank_a,
18-
phy.settings.dfi_d,
19-
phy.settings.nphases)
18+
phy_settings.dfi_d,
19+
phy_settings.nphases)
2020
self.lasmic = lasmibus.Interface(
2121
aw=geom_settings.row_a + geom_settings.col_a - address_align,
22-
dw=phy.settings.dfi_d*phy.settings.nphases,
22+
dw=phy_settings.dfi_d*phy_settings.nphases,
2323
nbanks=2**geom_settings.bank_a,
2424
req_queue_size=timing_settings.req_queue_size,
25-
read_latency=phy.settings.read_latency+1,
26-
write_latency=phy.settings.write_latency+1)
25+
read_latency=phy_settings.read_latency+1,
26+
write_latency=phy_settings.write_latency+1)
2727
self.nrowbits = geom_settings.col_a - address_align
2828

2929
###
@@ -33,7 +33,7 @@ def __init__(self, phy, geom_settings, timing_settings, **kwargs):
3333
self.submodules.bank_machines = [BankMachine(geom_settings, timing_settings, address_align, i,
3434
getattr(self.lasmic, "bank"+str(i)))
3535
for i in range(2**geom_settings.bank_a)]
36-
self.submodules.multiplexer = Multiplexer(phy, geom_settings, timing_settings,
36+
self.submodules.multiplexer = Multiplexer(phy_settings, geom_settings, timing_settings,
3737
self.bank_machines, self.refresher,
3838
self.dfi, self.lasmic,
3939
**kwargs)

Diff for: ‎misoclib/mem/sdram/core/lasmicon/multiplexer.py

+12-12
Original file line numberDiff line numberDiff line change
@@ -89,9 +89,9 @@ def stb_and(cmd, attr):
8989
]
9090

9191
class Multiplexer(Module, AutoCSR):
92-
def __init__(self, phy, geom_settings, timing_settings, bank_machines, refresher, dfi, lasmic,
92+
def __init__(self, phy_settings, geom_settings, timing_settings, bank_machines, refresher, dfi, lasmic,
9393
with_bandwidth=False):
94-
assert(phy.settings.nphases == len(dfi.phases))
94+
assert(phy_settings.nphases == len(dfi.phases))
9595

9696
# Command choosing
9797
requests = [bm.cmd for bm in bank_machines]
@@ -101,7 +101,7 @@ def __init__(self, phy, geom_settings, timing_settings, bank_machines, refresher
101101
choose_cmd.want_reads.eq(0),
102102
choose_cmd.want_writes.eq(0)
103103
]
104-
if phy.settings.nphases == 1:
104+
if phy_settings.nphases == 1:
105105
self.comb += [
106106
choose_cmd.want_cmds.eq(1),
107107
choose_req.want_cmds.eq(1)
@@ -159,19 +159,19 @@ def anti_starvation(timeout):
159159
fsm = FSM()
160160
self.submodules += fsm
161161

162-
def steerer_sel(steerer, phy, r_w_n):
162+
def steerer_sel(steerer, phy_settings, r_w_n):
163163
r = []
164-
for i in range(phy.settings.nphases):
164+
for i in range(phy_settings.nphases):
165165
s = steerer.sel[i].eq(STEER_NOP)
166166
if r_w_n == "read":
167-
if i == phy.settings.rdphase:
167+
if i == phy_settings.rdphase:
168168
s = steerer.sel[i].eq(STEER_REQ)
169-
elif i == phy.settings.rdcmdphase:
169+
elif i == phy_settings.rdcmdphase:
170170
s = steerer.sel[i].eq(STEER_CMD)
171171
elif r_w_n == "write":
172-
if i == phy.settings.wrphase:
172+
if i == phy_settings.wrphase:
173173
s = steerer.sel[i].eq(STEER_REQ)
174-
elif i == phy.settings.wrcmdphase:
174+
elif i == phy_settings.wrcmdphase:
175175
s = steerer.sel[i].eq(STEER_CMD)
176176
else:
177177
raise ValueError
@@ -183,7 +183,7 @@ def steerer_sel(steerer, phy, r_w_n):
183183
choose_req.want_reads.eq(1),
184184
choose_cmd.cmd.ack.eq(1),
185185
choose_req.cmd.ack.eq(1),
186-
steerer_sel(steerer, phy, "read"),
186+
steerer_sel(steerer, phy_settings, "read"),
187187
If(write_available,
188188
# TODO: switch only after several cycles of ~read_available?
189189
If(~read_available | max_read_time, NextState("RTW"))
@@ -195,7 +195,7 @@ def steerer_sel(steerer, phy, r_w_n):
195195
choose_req.want_writes.eq(1),
196196
choose_cmd.cmd.ack.eq(1),
197197
choose_req.cmd.ack.eq(1),
198-
steerer_sel(steerer, phy, "write"),
198+
steerer_sel(steerer, phy_settings, "write"),
199199
If(read_available,
200200
If(~write_available | max_write_time, NextState("WTR"))
201201
),
@@ -205,7 +205,7 @@ def steerer_sel(steerer, phy, r_w_n):
205205
steerer.sel[0].eq(STEER_REFRESH),
206206
If(~refresher.req, NextState("READ"))
207207
)
208-
fsm.delayed_enter("RTW", "WRITE", phy.settings.read_latency-1) # FIXME: reduce this, actual limit is around (cl+1)/nphases
208+
fsm.delayed_enter("RTW", "WRITE", phy_settings.read_latency-1) # FIXME: reduce this, actual limit is around (cl+1)/nphases
209209
fsm.delayed_enter("WTR", "READ", timing_settings.tWTR-1)
210210
# FIXME: workaround for zero-delay loop simulation problem with Icarus Verilog
211211
fsm.finalize()

Diff for: ‎misoclib/mem/sdram/core/minicon/__init__.py

+10-10
Original file line numberDiff line numberDiff line change
@@ -35,26 +35,26 @@ def col(self, address):
3535
return Cat(Replicate(0, self.address_align), address[:split])
3636

3737
class Minicon(Module):
38-
def __init__(self, phy, geom_settings, timing_settings):
39-
if phy.settings.memtype in ["SDR"]:
40-
burst_length = phy.settings.nphases*1 # command multiplication*SDR
41-
elif phy.settings.memtype in ["DDR", "LPDDR", "DDR2", "DDR3"]:
42-
burst_length = phy.settings.nphases*2 # command multiplication*DDR
38+
def __init__(self, phy_settings, geom_settings, timing_settings):
39+
if phy_settings.memtype in ["SDR"]:
40+
burst_length = phy_settings.nphases*1 # command multiplication*SDR
41+
elif phy_settings.memtype in ["DDR", "LPDDR", "DDR2", "DDR3"]:
42+
burst_length = phy_settings.nphases*2 # command multiplication*DDR
4343
address_align = log2_int(burst_length)
4444

4545
nbanks = range(2**geom_settings.bank_a)
4646
A10_ENABLED = 0
4747
COLUMN = 1
4848
ROW = 2
49-
rdphase = phy.settings.rdphase
50-
wrphase = phy.settings.wrphase
49+
rdphase = phy_settings.rdphase
50+
wrphase = phy_settings.wrphase
5151

5252
self.dfi = dfi = dfibus.Interface(geom_settings.mux_a,
5353
geom_settings.bank_a,
54-
phy.settings.dfi_d,
55-
phy.settings.nphases)
54+
phy_settings.dfi_d,
55+
phy_settings.nphases)
5656

57-
self.bus = bus = wishbone.Interface(data_width=phy.settings.nphases*flen(dfi.phases[rdphase].rddata))
57+
self.bus = bus = wishbone.Interface(data_width=phy_settings.nphases*flen(dfi.phases[rdphase].rddata))
5858
slicer = _AddressSlicer(geom_settings.col_a, geom_settings.bank_a, geom_settings.row_a, address_align)
5959
refresh_req = Signal()
6060
refresh_ack = Signal()

Diff for: ‎misoclib/mem/sdram/phy/initsequence.py

+16-16
Original file line numberDiff line numberDiff line change
@@ -1,10 +1,10 @@
11
from migen.fhdl.std import log2_int
22

3-
def get_sdram_phy_header(sdram_phy):
3+
def get_sdram_phy_header(sdram_phy_settings):
44
r = "#ifndef __GENERATED_SDRAM_PHY_H\n#define __GENERATED_SDRAM_PHY_H\n"
55
r += "#include <hw/common.h>\n#include <generated/csr.h>\n#include <hw/flags.h>\n\n"
66

7-
nphases = sdram_phy.settings.nphases
7+
nphases = sdram_phy_settings.nphases
88
r += "#define DFII_NPHASES "+str(nphases)+"\n\n"
99

1010
r += "static void cdelay(int i);\n"
@@ -29,7 +29,7 @@ def get_sdram_phy_header(sdram_phy):
2929
3030
#define command_prd(X) command_p{rdphase}(X)
3131
#define command_pwr(X) command_p{wrphase}(X)
32-
""".format(rdphase=str(sdram_phy.settings.rdphase), wrphase=str(sdram_phy.settings.wrphase))
32+
""".format(rdphase=str(sdram_phy_settings.rdphase), wrphase=str(sdram_phy_settings.wrphase))
3333
r +="\n"
3434

3535
#
@@ -64,10 +64,10 @@ def get_sdram_phy_header(sdram_phy):
6464
"CKE" : "DFII_CONTROL_CKE|DFII_CONTROL_ODT|DFII_CONTROL_RESET_N"
6565
}
6666

67-
cl = sdram_phy.settings.cl
67+
cl = sdram_phy_settings.cl
6868

69-
if sdram_phy.settings.memtype == "SDR":
70-
bl = sdram_phy.settings.nphases
69+
if sdram_phy_settings.memtype == "SDR":
70+
bl = sdram_phy_settings.nphases
7171
mr = log2_int(bl) + (cl << 4)
7272
reset_dll = 1 << 8
7373

@@ -81,8 +81,8 @@ def get_sdram_phy_header(sdram_phy):
8181
("Load Mode Register / CL={0:d}, BL={1:d}".format(cl, bl), mr, 0, cmds["MODE_REGISTER"], 200)
8282
]
8383

84-
elif sdram_phy.settings.memtype == "DDR":
85-
bl = 2*sdram_phy.settings.nphases
84+
elif sdram_phy_settings.memtype == "DDR":
85+
bl = 2*sdram_phy_settings.nphases
8686
mr = log2_int(bl) + (cl << 4)
8787
emr = 0
8888
reset_dll = 1 << 8
@@ -98,8 +98,8 @@ def get_sdram_phy_header(sdram_phy):
9898
("Load Mode Register / CL={0:d}, BL={1:d}".format(cl, bl), mr, 0, cmds["MODE_REGISTER"], 200)
9999
]
100100

101-
elif sdram_phy.settings.memtype == "LPDDR":
102-
bl = 2*sdram_phy.settings.nphases
101+
elif sdram_phy_settings.memtype == "LPDDR":
102+
bl = 2*sdram_phy_settings.nphases
103103
mr = log2_int(bl) + (cl << 4)
104104
emr = 0
105105
reset_dll = 1 << 8
@@ -115,8 +115,8 @@ def get_sdram_phy_header(sdram_phy):
115115
("Load Mode Register / CL={0:d}, BL={1:d}".format(cl, bl), mr, 0, cmds["MODE_REGISTER"], 200)
116116
]
117117

118-
elif sdram_phy.settings.memtype == "DDR2":
119-
bl = 2*sdram_phy.settings.nphases
118+
elif sdram_phy_settings.memtype == "DDR2":
119+
bl = 2*sdram_phy_settings.nphases
120120
wr = 2
121121
mr = log2_int(bl) + (cl << 4) + (wr << 9)
122122
emr = 0
@@ -139,8 +139,8 @@ def get_sdram_phy_header(sdram_phy):
139139
("Load Extended Mode Register / OCD Default", emr+ocd, 1, cmds["MODE_REGISTER"], 0),
140140
("Load Extended Mode Register / OCD Exit", emr, 1, cmds["MODE_REGISTER"], 0),
141141
]
142-
elif sdram_phy.settings.memtype == "DDR3":
143-
bl = 2*sdram_phy.settings.nphases
142+
elif sdram_phy_settings.memtype == "DDR3":
143+
bl = 2*sdram_phy_settings.nphases
144144
if bl != 8:
145145
raise NotImplementedError("DDR3 PHY header generator only supports BL of 8")
146146

@@ -188,7 +188,7 @@ def format_mr2(cwl, rtt_wr):
188188

189189
mr0 = format_mr0(cl, 8, 1) # wr=8 FIXME: this should be ceiling(tWR/tCK)
190190
mr1 = format_mr1(1, 1) # Output Drive Strength RZQ/7 (34 ohm) / Rtt RZQ/4 (60 ohm)
191-
mr2 = format_mr2(sdram_phy.settings.cwl, 2) # Rtt(WR) RZQ/4
191+
mr2 = format_mr2(sdram_phy_settings.cwl, 2) # Rtt(WR) RZQ/4
192192
mr3 = 0
193193

194194
init_sequence = [
@@ -204,7 +204,7 @@ def format_mr2(cwl, rtt_wr):
204204
# the value of MR1 needs to be modified during write leveling
205205
r += "#define DDR3_MR1 {}\n\n".format(mr1)
206206
else:
207-
raise NotImplementedError("Unsupported memory type: "+sdram_phy.settings.memtype)
207+
raise NotImplementedError("Unsupported memory type: "+sdram_phy_settings.memtype)
208208

209209
r += "static void init_sequence(void)\n{\n"
210210
for comment, a, ba, cmd, delay in init_sequence:

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