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targets/ppro: disable L2
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sbourdeauducq committed Feb 28, 2015
1 parent 0127de9 commit 7028d85
Showing 1 changed file with 2 additions and 1 deletion.
3 changes: 2 additions & 1 deletion soc/targets/artiq_ppro.py
Original file line number Diff line number Diff line change
@@ -92,7 +92,8 @@ class ARTIQMiniSoC(BaseSoC):
}
csr_map.update(BaseSoC.csr_map)

def __init__(self, platform, cpu_type="or1k", ramcon_type="minicon",
def __init__(self, platform, cpu_type="or1k",
ramcon_type="minicon", with_l2=False,
with_test_gen=False, **kwargs):
BaseSoC.__init__(self, platform,
cpu_type=cpu_type, ramcon_type=ramcon_type,

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