uart: generate ack for rx (serialboot OK with sim)

enjoy-digital · enjoy-digital · commit 200791c81d9c · 2015-03-04T00:57:37.000+01:00
diff --git a/misoclib/com/uart/__init__.py b/misoclib/com/uart/__init__.py
@@ -26,5 +26,6 @@ def __init__(self, phy):
 		]
 		self.comb += [
 			self.ev.tx.trigger.eq(phy.sink.stb & phy.sink.ack),
-			self.ev.rx.trigger.eq(phy.source.stb) #phy.source.ack supposed to be always 1
+			self.ev.rx.trigger.eq(phy.source.stb & phy.source.ack),
+			phy.source.ack.eq(~self.ev.rx.pending)
 		]
diff --git a/misoclib/com/uart/phy/sim.py b/misoclib/com/uart/phy/sim.py
@@ -12,5 +12,6 @@ def __init__(self, pads):
 			self.sink.ack.eq(pads.source_ack),
 
 			self.source.stb.eq(pads.sink_stb),
-			self.source.data.eq(pads.sink_data)
+			self.source.data.eq(pads.sink_data),
+			pads.sink_ack.eq(self.source.ack)
 		]

Original file line number	Diff line number	Diff line change
`@@ -26,5 +26,6 @@ def __init__(self, phy):`
`26`	`26`	`]`
`27`	`27`	`self.comb += [`
`28`	`28`	`self.ev.tx.trigger.eq(phy.sink.stb & phy.sink.ack),`
`29`		`- self.ev.rx.trigger.eq(phy.source.stb) #phy.source.ack supposed to be always 1`
	`29`	`+ self.ev.rx.trigger.eq(phy.source.stb & phy.source.ack),`
	`30`	`+ phy.source.ack.eq(~self.ev.rx.pending)`
`30`	`31`	`]`
Original file line number	Diff line number	Diff line change
`@@ -12,5 +12,6 @@ def __init__(self, pads):`
`12`	`12`	`self.sink.ack.eq(pads.source_ack),`
`13`	`13`
`14`	`14`	`self.source.stb.eq(pads.sink_stb),`
`15`		`- self.source.data.eq(pads.sink_data)`
	`15`	`+ self.source.data.eq(pads.sink_data),`
	`16`	`+ pads.sink_ack.eq(self.source.ack)`
`16`	`17`	`]`