Skip to content

Commit

Permalink
soc: remove is_sim function
Browse files Browse the repository at this point in the history
enjoy-digital committed Mar 3, 2015
1 parent 905be50 commit 0bcd6da
Showing 1 changed file with 1 addition and 7 deletions.
8 changes: 1 addition & 7 deletions misoclib/soc/__init__.py
Original file line number Diff line number Diff line change
@@ -15,12 +15,6 @@
def mem_decoder(address, start=26, end=29):
return lambda a: a[start:end] == ((address >> (start+2)) & (2**(end-start))-1)

def is_sim(platform):
if hasattr(platform, "is_sim"):
return platform.is_sim
else:
return False

class SoC(Module):
csr_map = {
"crg": 0, # user
@@ -114,7 +108,7 @@ def __init__(self, platform, clk_freq, cpu_or_bridge=None,
self.register_mem("csr", self.mem_map["csr"], self.wishbone2csr.wishbone)

if with_uart:
if is_sim(platform):
if getattr(platform, "is_sim", False):
self.submodules.uart_phy = UARTPHYSim(platform.request("serial"))
else:
self.submodules.uart_phy = UARTPHYSerial(platform.request("serial"), clk_freq, uart_baudrate)

0 comments on commit 0bcd6da

Please sign in to comment.