sdram: move lasmibus to core, rename crossbar to lasmixbar and move i…

…t to core, move dfi to phy
m-labs · Mar 3, 2015 · 905be50 · 905be50
1 parent 9210272
commit 905be50
Show file tree

Hide file tree

Showing 16 changed files with 16 additions and 16 deletions.
diff --git a/misoclib/mem/sdram/core/__init__.py b/misoclib/mem/sdram/core/__init__.py
@@ -4,7 +4,7 @@
 
 from misoclib.mem.sdram.phy import dfii
 from misoclib.mem.sdram.core import minicon, lasmicon
-from misoclib.mem.sdram.core.lasmicon.crossbar import Crossbar
+from misoclib.mem.sdram.core import lasmixbar
 
 class SDRAMCore(Module, AutoCSR):
 	def __init__(self, phy, ramcon_type, sdram_geom, sdram_timing, **kwargs):
@@ -18,7 +18,7 @@ def __init__(self, phy, ramcon_type, sdram_geom, sdram_timing, **kwargs):
 			self.submodules.controller = controller = lasmicon.LASMIcon(phy.settings, sdram_geom, sdram_timing, **kwargs)
 			self.comb += Record.connect(controller.dfi, self.dfii.slave)
 
-			self.submodules.crossbar = crossbar = Crossbar([controller.lasmic], controller.nrowbits)
+			self.submodules.crossbar = crossbar = lasmixbar.LASMIxbar([controller.lasmic], controller.nrowbits)
 
 		# MINICON
 		elif ramcon_type == "minicon":

diff --git a/misoclib/mem/sdram/bus/lasmibus.py → misoclib/mem/sdram/core/lasmibus.py b/misoclib/mem/sdram/bus/lasmibus.py → misoclib/mem/sdram/core/lasmibus.py
diff --git a/misoclib/mem/sdram/core/lasmicon/__init__.py b/misoclib/mem/sdram/core/lasmicon/__init__.py
@@ -1,6 +1,7 @@
 from migen.fhdl.std import *
 
-from misoclib.mem.sdram.bus import dfi, lasmibus
+from misoclib.mem.sdram.phy import dfi
+from misoclib.mem.sdram.core import lasmibus
 from misoclib.mem.sdram.core.lasmicon.refresher import *
 from misoclib.mem.sdram.core.lasmicon.bankmachine import *
 from misoclib.mem.sdram.core.lasmicon.multiplexer import *

diff --git a/misoclib/mem/sdram/core/lasmicon/crossbar.py → misoclib/mem/sdram/core/lasmixbar.py b/misoclib/mem/sdram/core/lasmicon/crossbar.py → misoclib/mem/sdram/core/lasmixbar.py
@@ -3,7 +3,7 @@
 from migen.genlib.record import *
 from migen.genlib.misc import optree
 
-from misoclib.mem.sdram.bus.lasmibus import Interface
+from misoclib.mem.sdram.core.lasmibus import Interface
 
 def _getattr_all(l, attr):
 	it = iter(l)
@@ -13,7 +13,7 @@ def _getattr_all(l, attr):
 			raise ValueError
 	return r
 
-class Crossbar(Module):
+class LASMIxbar(Module):
 	def __init__(self, controllers, cba_shift):
 		self._controllers = controllers
 		self._cba_shift = cba_shift

diff --git a/misoclib/mem/sdram/core/minicon/__init__.py b/misoclib/mem/sdram/core/minicon/__init__.py
@@ -2,7 +2,7 @@
 from migen.bus import wishbone
 from migen.genlib.fsm import FSM, NextState
 
-from misoclib.mem.sdram.bus import dfi as dfibus
+from misoclib.mem.sdram.phy import dfi as dfibus
 
 class _AddressSlicer:
 	def __init__(self, col_a, bank_a, row_a, address_align):

diff --git a/misoclib/mem/sdram/bus/dfi.py → misoclib/mem/sdram/phy/dfi.py b/misoclib/mem/sdram/bus/dfi.py → misoclib/mem/sdram/phy/dfi.py
diff --git a/misoclib/mem/sdram/phy/dfii.py b/misoclib/mem/sdram/phy/dfii.py
@@ -1,7 +1,7 @@
 from migen.fhdl.std import *
 from migen.bank.description import *
 
-from misoclib.mem.sdram.bus import dfi
+from misoclib.mem.sdram.phy import dfi
 
 class PhaseInjector(Module, AutoCSR):
 	def __init__(self, phase):

diff --git a/misoclib/mem/sdram/phy/gensdrphy.py b/misoclib/mem/sdram/phy/gensdrphy.py
@@ -25,7 +25,7 @@
 from migen.genlib.record import *
 from migen.fhdl.specials import *
 
-from misoclib.mem.sdram.bus.dfi import *
+from misoclib.mem.sdram.phy.dfi import *
 from misoclib.mem import sdram
 
 class GENSDRPHY(Module):

diff --git a/misoclib/mem/sdram/phy/k7ddrphy.py b/misoclib/mem/sdram/phy/k7ddrphy.py
@@ -3,7 +3,7 @@
 from migen.fhdl.std import *
 from migen.bank.description import *
 
-from misoclib.mem.sdram.bus.dfi import *
+from misoclib.mem.sdram.phy.dfi import *
 from misoclib.mem import sdram
 
 class K7DDRPHY(Module, AutoCSR):

diff --git a/misoclib/mem/sdram/phy/s6ddrphy.py b/misoclib/mem/sdram/phy/s6ddrphy.py
@@ -17,7 +17,7 @@
 from migen.fhdl.std import *
 from migen.genlib.record import *
 
-from misoclib.mem.sdram.bus.dfi import *
+from misoclib.mem.sdram.phy.dfi import *
 from misoclib.mem import sdram
 
 class S6DDRPHY(Module):

diff --git a/misoclib/mem/sdram/test/abstract_transactions_lasmi.py b/misoclib/mem/sdram/test/abstract_transactions_lasmi.py
@@ -2,7 +2,7 @@
 from migen.bus.transactions import *
 from migen.sim.generic import run_simulation
 
-from misoclib.mem.sdram.bus import lasmibus
+from misoclib.mem.sdram.core import lasmibus
 
 def my_generator(n):
 	bank = n % 4

diff --git a/misoclib/mem/sdram/test/bankmachine_tb.py b/misoclib/mem/sdram/test/bankmachine_tb.py
@@ -1,7 +1,7 @@
 from migen.fhdl.std import *
 from migen.sim.generic import run_simulation
 
-from misoclib.mem.sdram.bus import lasmibus
+from misoclib.mem.sdram.code import lasmibus
 from misoclib.mem.sdram.core.lasmicon.bankmachine import *
 
 from common import sdram_phy, sdram_geom, sdram_timing, CommandLogger

diff --git a/misoclib/mem/sdram/test/lasmicon_df_tb.py b/misoclib/mem/sdram/test/lasmicon_df_tb.py
@@ -1,7 +1,7 @@
 from migen.fhdl.std import *
 from migen.sim.generic import run_simulation
 
-from misoclib.mem.sdram.bus import lasmibus
+from misoclib.mem.sdram.core import lasmibus
 from misoclib.mem.sdram.core.lasmicon import *
 from misoclib.mem.sdram.frontend import dma_lasmi
 

diff --git a/misoclib/mem/sdram/test/lasmicon_tb.py b/misoclib/mem/sdram/test/lasmicon_tb.py
@@ -1,7 +1,7 @@
 from migen.fhdl.std import *
 from migen.sim.generic import run_simulation
 
-from misoclib.mem.sdram.bus import lasmibus
+from misoclib.mem.sdram.core import lasmibus
 from misoclib.mem.sdram.core.lasmicon import *
 
 from common import sdram_phy, sdram_geom, sdram_timing, DFILogger

diff --git a/misoclib/mem/sdram/test/lasmicon_wb.py b/misoclib/mem/sdram/test/lasmicon_wb.py
@@ -3,7 +3,7 @@
 from migen.bus.transactions import *
 from migen.sim.generic import run_simulation
 
-from misoclib.mem.sdram.bus import lasmibus
+from misoclib.mem.sdram.core import lasmibus
 from misoclib.mem.sdram.core.lasmicon import *
 from misoclib.mem.sdram.frontend import wishbone2lasmi
 

diff --git a/misoclib/soc/sdram.py b/misoclib/soc/sdram.py
@@ -2,7 +2,6 @@
 from migen.bus import wishbone, csr
 from migen.genlib.record import *
 
-from misoclib.mem.sdram.bus import dfi, lasmibus
 from misoclib.mem.sdram.core import SDRAMCore
 from misoclib.mem.sdram.frontend import memtest, wishbone2lasmi
 from misoclib.soc import SoC, mem_decoder