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base repository: m-labs/misoc
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  • 3 commits
  • 8 files changed
  • 1 contributor

Commits on Mar 3, 2015

  1. Copy the full SHA
    f27e7a4 View commit details
  2. Copy the full SHA
    1d4dc45 View commit details
  3. targets: keep the SPI flash core even if with_rom is enabled, so that…

    … flash booting in the BIOS still works
    enjoy-digital committed Mar 3, 2015
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    0716dad View commit details
6 changes: 3 additions & 3 deletions misoclib/com/liteeth/example_designs/test/test_regs.py
Original file line number Diff line number Diff line change
@@ -2,9 +2,9 @@ def main(wb):
wb.open()
regs = wb.regs
###
print("sysid : 0x%04x" %regs.identifier_sysid.read())
print("revision : 0x%04x" %regs.identifier_revision.read())
print("frequency : %d MHz" %(regs.identifier_frequency.read()/1000000))
print("sysid : 0x{:04x}".format(regs.identifier_sysid.read()))
print("revision : 0x{:04x}".format(regs.identifier_revision.read()))
print("frequency : 0x{:04x}MHz".format(regs.identifier_frequency.read()/1000000))
SRAM_BASE = 0x02000000
wb.write(SRAM_BASE, [i for i in range(64)])
print(wb.read(SRAM_BASE, 64))
4 changes: 0 additions & 4 deletions misoclib/mem/litesata/example_designs/platforms/kc705.py
Original file line number Diff line number Diff line change
@@ -33,10 +33,6 @@ def do_finalize(self, fragment):
self.add_period_constraint(self.lookup_request("clk200").p, 5.0)
except ConstraintError:
pass
try:
self.add_period_constraint(self.lookup_request("sata_host").refclk_p, 6.66)
except ConstraintError:
pass
self.add_platform_command("""
create_clock -name sys_clk -period 6 [get_nets sys_clk]
create_clock -name sata_rx_clk -period 3.33 [get_nets sata_rx_clk]
6 changes: 3 additions & 3 deletions misoclib/mem/litesata/example_designs/test/test_regs.py
Original file line number Diff line number Diff line change
@@ -2,8 +2,8 @@ def main(wb):
wb.open()
regs = wb.regs
###
print("sysid : 0x%04x" %regs.identifier_sysid.read())
print("revision : 0x%04x" %regs.identifier_revision.read())
print("frequency : %d MHz" %(regs.identifier_frequency.read()/1000000))
print("sysid : 0x{:04x}".format(regs.identifier_sysid.read()))
print("revision : 0x{:04x}".format(regs.identifier_revision.read()))
print("frequency : 0x{:04x}MHz".format(regs.identifier_frequency.read()/1000000))
###
wb.close()
6 changes: 3 additions & 3 deletions misoclib/tools/litescope/example_designs/test/test_regs.py
Original file line number Diff line number Diff line change
@@ -2,8 +2,8 @@ def main(wb):
wb.open()
regs = wb.regs
###
print("sysid : 0x%04x" %regs.identifier_sysid.read())
print("revision : 0x%04x" %regs.identifier_revision.read())
print("frequency : %d MHz" %(regs.identifier_frequency.read()/1000000))
print("sysid : 0x{:04x}".format(regs.identifier_sysid.read()))
print("revision : 0x{:04x}".format(regs.identifier_revision.read()))
print("frequency : 0x{:04x}MHz".format(regs.identifier_frequency.read()/1000000))
###
wb.close()
15 changes: 8 additions & 7 deletions targets/kc705.py
Original file line number Diff line number Diff line change
@@ -100,15 +100,16 @@ def __init__(self, platform, **kwargs):
self.submodules.ddrphy = k7ddrphy.K7DDRPHY(platform.request("ddram"), memtype="DDR3")
self.register_sdram_phy(self.ddrphy, sdram_geom, sdram_timing)

spiflash_pads = platform.request("spiflash")
spiflash_pads.clk = Signal()
self.specials += Instance("STARTUPE2",
i_CLK=0, i_GSR=0, i_GTS=0, i_KEYCLEARB=0, i_PACK=0,
i_USRCCLKO=spiflash_pads.clk, i_USRCCLKTS=0, i_USRDONEO=1, i_USRDONETS=1)
self.submodules.spiflash = spiflash.SpiFlash(spiflash_pads, dummy=11, div=2)
self.flash_boot_address = 0xb00000

# If not in ROM, BIOS is in SPI flash
if not self.with_rom:
spiflash_pads = platform.request("spiflash")
spiflash_pads.clk = Signal()
self.specials += Instance("STARTUPE2",
i_CLK=0, i_GSR=0, i_GTS=0, i_KEYCLEARB=0, i_PACK=0,
i_USRCCLKO=spiflash_pads.clk, i_USRCCLKTS=0, i_USRDONEO=1, i_USRDONETS=1)
self.submodules.spiflash = spiflash.SpiFlash(spiflash_pads, dummy=11, div=2)
self.flash_boot_address = 0xb00000
self.register_rom(self.spiflash.bus)

class MiniSoC(BaseSoC):
7 changes: 4 additions & 3 deletions targets/mlabs_video.py
Original file line number Diff line number Diff line change
@@ -59,11 +59,12 @@ def __init__(self, platform, **kwargs):
rd_bitslip=0, wr_bitslip=3, dqs_ddr_alignment="C1")
self.register_sdram_phy(self.ddrphy, sdram_geom, sdram_timing)

self.submodules.norflash = norflash16.NorFlash16(platform.request("norflash"),
self.ns(110), self.ns(50))
self.flash_boot_address = 0x001a0000

# If not in ROM, BIOS is in // NOR flash
if not self.with_rom:
self.submodules.norflash = norflash16.NorFlash16(platform.request("norflash"),
self.ns(110), self.ns(50))
self.flash_boot_address = 0x001a0000
self.register_rom(self.norflash.bus)

self.submodules.crg = mxcrg.MXCRG(_MXClockPads(platform), self.clk_freq)
6 changes: 4 additions & 2 deletions targets/pipistrello.py
Original file line number Diff line number Diff line change
@@ -122,10 +122,12 @@ def __init__(self, platform, **kwargs):
PIN "BUFG.O" CLOCK_DEDICATED_ROUTE = FALSE;
""")
self.register_sdram_phy(self.ddrphy, sdram_geom, sdram_timing)

self.submodules.spiflash = spiflash.SpiFlash(platform.request("spiflash4x"), dummy=11, div=2)
self.flash_boot_address = 0x180000

# If not in ROM, BIOS is in SPI flash
if not self.with_rom:
self.submodules.spiflash = spiflash.SpiFlash(platform.request("spiflash4x"), dummy=11, div=2)
self.flash_boot_address = 0x180000
self.register_rom(self.spiflash.bus)

default_subtarget = BaseSoC
5 changes: 3 additions & 2 deletions targets/ppro.py
Original file line number Diff line number Diff line change
@@ -92,10 +92,11 @@ def __init__(self, platform, **kwargs):
self.submodules.sdrphy = gensdrphy.GENSDRPHY(platform.request("sdram"))
self.register_sdram_phy(self.sdrphy, sdram_geom, sdram_timing)

self.submodules.spiflash = spiflash.SpiFlash(platform.request("spiflash2x"), dummy=4, div=6)
self.flash_boot_address = 0x70000

# If not in ROM, BIOS is in SPI flash
if not self.with_rom:
self.submodules.spiflash = spiflash.SpiFlash(platform.request("spiflash2x"), dummy=4, div=6)
self.flash_boot_address = 0x70000
self.register_rom(self.spiflash.bus)

default_subtarget = BaseSoC