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base repository: m-labs/migen
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  • 7 commits
  • 3 files changed
  • 3 contributors

Commits on Feb 26, 2015

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    28c219e View commit details

Commits on Feb 27, 2015

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    ba26a40 View commit details
  2. add pipistrello platform

    jordens authored and sbourdeauducq committed Feb 27, 2015
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    5b5d2d1 View commit details
  3. add fpgaprog programmer

    jordens authored and sbourdeauducq committed Feb 27, 2015
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  4. pipistrello: use fpgaprog

    jordens authored and sbourdeauducq committed Feb 27, 2015
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Showing with 186 additions and 1 deletion.
  1. +39 −0 mibuild/platforms/kc705.py
  2. +128 −0 mibuild/platforms/pipistrello.py
  3. +19 −1 mibuild/xilinx/programmer.py
39 changes: 39 additions & 0 deletions mibuild/platforms/kc705.py
Original file line number Diff line number Diff line change
@@ -28,6 +28,11 @@
("user_dip_btn", 2, Pins("AA28"), IOStandard("LVCMOS25")),
("user_dip_btn", 3, Pins("Y28"), IOStandard("LVCMOS25")),

("user_sma_clock", 0,
Subsignal("p", Pins("L25"), IOStandard("LVDS_25")),
Subsignal("n", Pins("K25"), IOStandard("LVDS_25"))
),

("clk200", 0,
Subsignal("p", Pins("AD12"), IOStandard("LVDS")),
Subsignal("n", Pins("AD11"), IOStandard("LVDS"))
@@ -335,6 +340,40 @@
"LA30_N": "AB30",
"LA32_P": "Y30",
"LA32_N": "AA30",
"LA06_P": "AK20",
"LA06_N": "AK21",
"LA10_P": "AJ24",
"LA10_N": "AK25",
"LA14_P": "AD21",
"LA14_N": "AE21",
"LA18_CC_P": "AD27",
"LA18_CC_N": "AD28",
"LA27_P": "AJ28",
"LA27_N": "AJ29",
"CLK1_M2C_P": "AG29",
"CLK1_M2C_N": "AH29",
"LA0_CC_P": "AD23",
"LA0_CC_N": "AE24",
"LA03_P": "AG20",
"LA03_N": "AH20",
"LA08_P": "AJ22",
"LA08_N": "AJ23",
"LA12_P": "AA20",
"LA12_N": "AB20",
"LA16_P": "AC22",
"LA16_N": "AD22",
"LA20_P": "AF26",
"LA20_N": "AF27",
"LA22_P": "AJ27",
"LA22_N": "AK28",
"LA25_P": "AC26",
"LA25_N": "AD26",
"LA29_P": "AE28",
"LA29_N": "AF28",
"LA31_P": "AD29",
"LA31_N": "AE29",
"LA33_P": "AC29",
"LA33_N": "AC30",
}
)
]
128 changes: 128 additions & 0 deletions mibuild/platforms/pipistrello.py
Original file line number Diff line number Diff line change
@@ -0,0 +1,128 @@
from mibuild.generic_platform import *
from mibuild.crg import SimpleCRG
from mibuild.xilinx.ise import XilinxISEPlatform
from mibuild.xilinx.programmer import FpgaProg

_io = [
("user_led", 0, Pins("V16"), IOStandard("LVTTL"), Drive(8), Misc("SLEW=QUIETIO")), # green near hdmi
("user_led", 1, Pins("U16"), IOStandard("LVTTL"), Drive(8), Misc("SLEW=QUIETIO")), # red near hdmi
("user_led", 2, Pins("A16"), IOStandard("LVTTL"), Drive(8), Misc("SLEW=QUIETIO")), # green at msd
("user_led", 3, Pins("A15"), IOStandard("LVTTL"), Drive(8), Misc("SLEW=QUIETIO")), # red at msd
("user_led", 4, Pins("A12"), IOStandard("LVTTL"), Drive(8), Misc("SLEW=QUIETIO")), # red at usb

("user_switch", 0, Pins("N14"), IOStandard("LVTTL"), Misc("PULLDOWN")),

("clk50", 0, Pins("H17"), IOStandard("LVTTL")),

("serial", 0,
Subsignal("tx", Pins("A10"), Misc("SLEW=SLOW")),
Subsignal("rx", Pins("A11"), Misc("PULLUP")),
Subsignal("rts", Pins("C10"), Misc("SLEW=SLOW")),
Subsignal("cts", Pins("A9"), Misc("PULLUP")),
IOStandard("LVTTL"),
),

("usb_fifo", 0,
Subsignal("data", Pins("A11 A10 C10 A9 B9 A8 B8 A7")),
Subsignal("rxf", Pins("C7")),
Subsignal("txe", Pins("A6")),
Subsignal("rd", Pins("B6")),
Subsignal("wr", Pins("A5")),
Subsignal("siwua", Pins("C5")),
IOStandard("LVTTL"),
),

("dvi_in", 0,
Subsignal("clk_p", Pins("U5"), IOStandard("TMDS_33")),
Subsignal("clk_n", Pins("V5"), IOStandard("TMDS_33")),
Subsignal("data0_p", Pins("T6"), IOStandard("TMDS_33")),
Subsignal("data0_n", Pins("V6"), IOStandard("TMDS_33")),
Subsignal("data1_p", Pins("U7"), IOStandard("TMDS_33")),
Subsignal("data1_n", Pins("V7"), IOStandard("TMDS_33")),
Subsignal("data2_p", Pins("U8"), IOStandard("TMDS_33")),
Subsignal("data2_n", Pins("V8"), IOStandard("TMDS_33")),
Subsignal("scl", Pins("V9"), IOStandard("LVCMOS33")),
Subsignal("sda", Pins("T9"), IOStandard("LVCMOS33")),
Subsignal("hpd_notif", Pins("R8"), IOStandard("LVCMOS33")),
),

("spiflash", 0,
Subsignal("cs_n", Pins("V3")),
Subsignal("clk", Pins("R15")),
Subsignal("mosi", Pins("T13")),
Subsignal("miso", Pins("R13"), Misc("PULLUP")),
Subsignal("wp", Pins("T14")),
Subsignal("hold", Pins("V14")),
IOStandard("LVTTL"), Misc("SLEW=FAST")
),

("spiflash2x", 0,
Subsignal("cs_n", Pins("V3")),
Subsignal("clk", Pins("R15")),
Subsignal("dq", Pins("T13", "R13"), Misc("PULLUP")),
Subsignal("wp", Pins("T14")),
Subsignal("hold", Pins("V14")),
IOStandard("LVCMOS33"), Misc("SLEW=FAST")
),

("mmc", 0,
Subsignal("clk", Pins("A3")),
Subsignal("cmd", Pins("B3")),
Subsignal("dat", Pins("B4 A4 B2 A2")),
IOStandard("SDIO")
),

("audio", 0,
Subsignal("l", Pins("R7")),
Subsignal("r", Pins("T7")),
IOStandard("LVTTL"),
),

("pmod", 0,
Subsignal("d", Pins("D9 C8 D6 C4 B11 C9 D8 C6")),
IOStandard("LVCMOS33")
),

("sdram_clock", 0,
Subsignal("p", Pins("G3")),
Subsignal("n", Pins("G1")),
IOStandard("MOBILE_DDR"), Misc("SLEW=FAST"),
),

("sdram", 0,
Subsignal("a", Pins("J7 J6 H5 L7 F3 H4 H3 H6 D2 D1 F4 D3 G6")),
Subsignal("ba", Pins("F2 F1")),
# Subsignal("cs_n", Pins("")),
Subsignal("cke", Pins("H7")),
Subsignal("ras_n", Pins("L5")),
Subsignal("cas_n", Pins("K5")),
Subsignal("we_n", Pins("E3")),
Subsignal("dq", Pins("L2 L1 K2 K1 H2 H1 J3 J1 M3 M1 N2 N1 T2 T1 U2 U1")),
Subsignal("dm", Pins("K3 K4")),
IOStandard("MOBILE_DDR"), Misc("SLEW=FAST")
)
]

_connectors = [
("A", "U18 T17 P17 P16 N16 N17 M16 L15 L17 K15 K17 J16 H15 H18 F18 D18"),
("B", "C18 E18 G18 H16 J18 K18 K16 L18 L16 M18 N18 N15 P15 P18 T18 U17"),
("C", "F17 F16 E16 G16 F15 G14 F14 H14 H13 J13 G13 H12 K14 K13 K12 L12"),
]

class Platform(XilinxISEPlatform):
identifier = 0x5049
default_clk_name = "clk50"
default_clk_period = 20

def __init__(self):
XilinxISEPlatform.__init__(self, "xc6slx45-csg324-2", _io,
lambda p: SimpleCRG(p, "clk50", None), _connectors)

def create_programmer(self):
return FpgaProg("bscan_spi_lx45_csg324.bit")

def do_finalize(self, fragment):
try:
self.add_period_constraint(self.lookup_request("clk50"), 20.)
except ConstraintError:
pass
20 changes: 19 additions & 1 deletion mibuild/xilinx/programmer.py
Original file line number Diff line number Diff line change
@@ -35,7 +35,7 @@ class XC3SProg(GenericProgrammer):
needs_bitreverse = False

def __init__(self, cable, flash_proxy_basename=None):
Programmer.__init__(self, flash_proxy_basename)
GenericProgrammer.__init__(self, flash_proxy_basename)
self.cable = cable

def load_bitstream(self, bitstream_file):
@@ -45,6 +45,24 @@ def flash(self, address, data_file):
flash_proxy = self.find_flash_proxy()
subprocess.call(["xc3sprog", "-v", "-c", self.cable, "-I"+flash_proxy, "{}:w:0x{:x}:BIN".format(data_file, address)])


class FpgaProg(GenericProgrammer):
needs_bitreverse = False

def __init__(self, flash_proxy_basename=None):
GenericProgrammer.__init__(self, flash_proxy_basename)

def load_bitstream(self, bitstream_file):
subprocess.call(["fpgaprog", "-v", "-f", bitstream_file])

def flash(self, address, data_file):
if address != 0:
raise ValueError("fpga prog needs a main bitstream at address 0")
flash_proxy = self.find_flash_proxy()
subprocess.call(["fpgaprog", "-v", "-sa", "-r", "-b", flash_proxy,
"-f", data_file])


def _run_vivado(cmds):
with subprocess.Popen("vivado -mode tcl", stdin=subprocess.PIPE, shell=True) as process:
process.stdin.write(cmds.encode("ASCII"))