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base repository: m-labs/misoc
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head repository: m-labs/misoc
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Commits on Aug 12, 2012

  1. - init Repo

    @enjoy-digital
    enjoy-digital committed Aug 12, 2012
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  2. add Readme

    @enjoy-digital
    enjoy-digital committed Aug 12, 2012
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  3. add Readme

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    enjoy-digital committed Aug 12, 2012
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  4. add simple Sequencer

    @enjoy-digital
    enjoy-digital committed Aug 12, 2012
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  5. rename Recorder --> Storage 

    add Recorder
    @enjoy-digital
    enjoy-digital committed Aug 12, 2012
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  6. add Trigger

    @enjoy-digital
    enjoy-digital committed Aug 12, 2012
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  7. fix masks on EdgeDetector

    @enjoy-digital
    enjoy-digital committed Aug 12, 2012
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  8. simplify EdgeDetector

    @enjoy-digital
    enjoy-digital committed Aug 12, 2012
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  9. add register interface to Trigger

    @enjoy-digital
    enjoy-digital committed Aug 12, 2012
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  10. new library spi2Csr (skeleton)

    @enjoy-digital
    enjoy-digital committed Aug 12, 2012
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Commits on Aug 22, 2012

  1. Add simulation skeleton 

    Remove SRLC16E, will be replaced by distributed ram
    @enjoy-digital
    enjoy-digital committed Aug 22, 2012
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Commits on Aug 23, 2012

  1. use ram for Sum

    @enjoy-digital
    enjoy-digital committed Aug 23, 2012
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Commits on Aug 25, 2012

  1. add sim: tb_TriggerCsr.py

    @enjoy-digital
    enjoy-digital committed Aug 25, 2012
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  2. add sim: tb_Spi2Csr.py (skeleton, WIP)

    @enjoy-digital
    enjoy-digital committed Aug 25, 2012
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  3. - fix Spi2Csr mistakes

    @enjoy-digital
    enjoy-digital committed Aug 25, 2012
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Commits on Aug 26, 2012

  1. tb_spi2Csr: Add clk_ratio 

    tb_spi2Csr: Add Read
spi2Csr : fixs
    @enjoy-digital
    enjoy-digital committed Aug 26, 2012
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  2. add truth table generator

    @enjoy-digital
    enjoy-digital committed Aug 26, 2012
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  3. tb_TriggerCsr.py : use truth table generator for Sum Lut

    @enjoy-digital
    enjoy-digital committed Aug 26, 2012
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  4. add vcd generator

    @enjoy-digital
    enjoy-digital committed Aug 26, 2012
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  5. split migScope to trigger & recorder

    @enjoy-digital
    enjoy-digital committed Aug 26, 2012
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  6. add tb_RecorderCsr.py 

    fixs in recorder.py
    @enjoy-digital
    enjoy-digital committed Aug 26, 2012
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Commits on Sep 9, 2012

  1. simplify registers mgnt

    @enjoy-digital
    enjoy-digital committed Sep 9, 2012
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  2. add global tb, fix bugs

    @enjoy-digital
    enjoy-digital committed Sep 9, 2012
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  3. Clean up

    @enjoy-digital
    enjoy-digital committed Sep 9, 2012
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  4. Initialize de0_nano example

    @enjoy-digital
    enjoy-digital committed Sep 9, 2012
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  5. Wip de0_nano example

    @enjoy-digital
    enjoy-digital committed Sep 9, 2012
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  6. Wip de0_nano example

    @enjoy-digital
    enjoy-digital committed Sep 9, 2012
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  7. Clean up

    @enjoy-digital
    enjoy-digital committed Sep 9, 2012
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Commits on Sep 12, 2012

  1. examples/de0_nano : add load cmd / change rst polarity

    @enjoy-digital
    enjoy-digital committed Sep 12, 2012
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  2. initialize de1 example

    @enjoy-digital
    enjoy-digital committed Sep 12, 2012
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  3. examples/de1: fix top

    @enjoy-digital
    enjoy-digital committed Sep 12, 2012
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  4. update README

    @enjoy-digital
    enjoy-digital committed Sep 12, 2012
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  5. add MigIo Class

    @enjoy-digital
    enjoy-digital committed Sep 12, 2012
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  6. examples/de1: use of MigIo

    @enjoy-digital
    enjoy-digital committed Sep 12, 2012
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Commits on Sep 13, 2012

  1. add spi2Csr tools : Python Host & Arduino Uart<-->Spi bridge

    @enjoy-digital
    enjoy-digital committed Sep 13, 2012
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  2. add address parameter to migIo

    @enjoy-digital
    enjoy-digital committed Sep 13, 2012
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  3. fix write function

    @enjoy-digital
    enjoy-digital committed Sep 13, 2012
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  4. add test_MigIo.py for de0_nano and de1 example

    @enjoy-digital
    enjoy-digital committed Sep 13, 2012
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Commits on Sep 14, 2012

  1. migScope/tools/truthtable.py: add function to remove duplicate operands

    @enjoy-digital
    enjoy-digital committed Sep 14, 2012
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  2. add access methods

    @enjoy-digital
    enjoy-digital committed Sep 14, 2012
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  3. add test_MigLa.py (Wip) 

    fixes
    @enjoy-digital
    enjoy-digital committed Sep 14, 2012
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  4. fixes & clean up

    @enjoy-digital
    enjoy-digital committed Sep 14, 2012
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Commits on Sep 15, 2012

  1. remove buggy workaround on read

    @enjoy-digital
    enjoy-digital committed Sep 15, 2012
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  2. fix bug put_ptr on start, separate put / get processes

    @enjoy-digital
    enjoy-digital committed Sep 15, 2012
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  3. examples/de1 : add ramp / square mode

    @enjoy-digital
    enjoy-digital committed Sep 15, 2012
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Commits on Sep 16, 2012

  1. simplify recorder

    @enjoy-digital
    enjoy-digital committed Sep 16, 2012
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  2. add ramp / square / sinus signal generation in examples

    @enjoy-digital
    enjoy-digital committed Sep 16, 2012
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  3. update README

    @enjoy-digital
    enjoy-digital committed Sep 16, 2012
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Commits on Sep 17, 2012

  1. use of new migen clock_domains convention

    @enjoy-digital
    enjoy-digital committed Sep 17, 2012
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  2. new MigLa Class, simplify & clean up

    @enjoy-digital
    enjoy-digital committed Sep 17, 2012
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