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gensoc: parameter check is now more restrictive, add additional info …
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…to help user
enjoy-digital committed Feb 28, 2015
1 parent 8e04ef7 commit 6b93849
Showing 1 changed file with 3 additions and 3 deletions.
6 changes: 3 additions & 3 deletions misoclib/gensoc/__init__.py
Original file line number Diff line number Diff line change
@@ -246,17 +246,17 @@ def register_sdram_phy(self, phy_dfi, phy_settings, sdram_geom, sdram_timing):
# MINICON
elif self.ramcon_type == "minicon":
if self.with_l2:
raise ValueError("MINICON does not implement L2 cache (Use LASMICON)")
raise ValueError("MINICON does not implement L2 cache (Use LASMICON or disable L2 cache (with_l2=False))")

self.submodules.minicon = sdramcon = Minicon(phy_settings, sdram_geom, sdram_timing)
self.submodules.dficon1 = dfi.Interconnect(sdramcon.dfi, self.dfii.slave)
sdram_width = flen(sdramcon.bus.dat_r)

sdram_size = 2**(sdram_geom.bank_a+sdram_geom.row_a+sdram_geom.col_a)*sdram_width//8

if (sdram_width == 32):
if sdram_width == 32:
self.register_mem("sdram", self.mem_map["sdram"], sdramcon.bus, sdram_size)
elif (sdram_width < 32):
elif sdram_width < 32:
self.submodules.dc = wishbone.DownConverter(32, sdram_width)
self.submodules.intercon = wishbone.InterconnectPointToPoint(self.dc.wishbone_o, sdramcon.bus)
self.register_mem("sdram", self.mem_map["sdram"], self.dc.wishbone_i, sdram_size)

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