LiteXXX cores: fix test_reg.py

m-labs · Mar 4, 2015 · 52f1c45 · 52f1c45
1 parent 60e87f6
commit 52f1c45
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Showing 3 changed files with 3 additions and 3 deletions.
diff --git a/misoclib/com/liteeth/example_designs/test/test_regs.py b/misoclib/com/liteeth/example_designs/test/test_regs.py
@@ -4,7 +4,7 @@ def main(wb):
 	###
 	print("sysid     : 0x{:04x}".format(regs.identifier_sysid.read()))
 	print("revision  : 0x{:04x}".format(regs.identifier_revision.read()))
-	print("frequency : 0x{:04x}MHz".format(regs.identifier_frequency.read()/1000000))
+	print("frequency : 0x{:04x}MHz".format(int(regs.identifier_frequency.read()/1000000)))
 	SRAM_BASE = 0x02000000
 	wb.write(SRAM_BASE, [i for i in range(64)])
 	print(wb.read(SRAM_BASE, 64))

diff --git a/misoclib/mem/litesata/example_designs/test/test_regs.py b/misoclib/mem/litesata/example_designs/test/test_regs.py
@@ -4,6 +4,6 @@ def main(wb):
 	###
 	print("sysid     : 0x{:04x}".format(regs.identifier_sysid.read()))
 	print("revision  : 0x{:04x}".format(regs.identifier_revision.read()))
-	print("frequency : 0x{:04x}MHz".format(regs.identifier_frequency.read()/1000000))
+	print("frequency : 0x{:04x}MHz".format(int(regs.identifier_frequency.read()/1000000)))
 	###
 	wb.close()
diff --git a/misoclib/tools/litescope/example_designs/test/test_regs.py b/misoclib/tools/litescope/example_designs/test/test_regs.py
@@ -4,6 +4,6 @@ def main(wb):
 	###
 	print("sysid     : 0x{:04x}".format(regs.identifier_sysid.read()))
 	print("revision  : 0x{:04x}".format(regs.identifier_revision.read()))
-	print("frequency : 0x{:04x}MHz".format(regs.identifier_frequency.read()/1000000))
+	print("frequency : 0x{:04x}MHz".format(int(regs.identifier_frequency.read()/1000000)))
 	###
 	wb.close()