m-labs · Mar 2, 2015 · Mar 2, 2015 · Mar 2, 2015 · Mar 2, 2015 · Mar 2, 2015
diff --git a/misoclib/mem/sdram/core/__init__.py b/misoclib/mem/sdram/core/__init__.py
@@ -0,0 +1,27 @@
+from migen.fhdl.std import *
+from migen.genlib.record import *
+from migen.bank.description import *
+
+from misoclib.mem.sdram.phy import dfii
+from misoclib.mem.sdram.core import minicon, lasmicon
+from misoclib.mem.sdram.core.lasmicon.crossbar import Crossbar
+
+class SDRAMCore(Module, AutoCSR):
+	def __init__(self, phy, ramcon_type, sdram_geom, sdram_timing):
+		# DFI
+		self.submodules.dfii = dfii.DFIInjector(phy, sdram_geom.mux_a, sdram_geom.bank_a)
+		self.comb += Record.connect(self.dfii.master, phy.dfi)
+
+		# LASMICON
+		if ramcon_type == "lasmicon":
+			self.submodules.controller = controller = lasmicon.LASMIcon(phy, sdram_geom, sdram_timing)
+			self.comb += Record.connect(controller.dfi, self.dfii.slave)
+
+			self.submodules.crossbar = crossbar = Crossbar([controller.lasmic], controller.nrowbits)
+
+		# MINICON
+		elif ramcon_type == "minicon":
+			self.submodules.controller = controller = minicon.Minicon(phy, sdram_geom, sdram_timing)
+			self.comb += Record.connect(controller.dfi, self.dfii.slave)
+		else:
+			raise ValueError("Unsupported SDRAM controller type: {}".format(self.ramcon_type))
diff --git a/misoclib/mem/sdram/lasmicon/__init__.py → misoclib/mem/sdram/core/lasmicon/__init__.py b/misoclib/mem/sdram/lasmicon/__init__.py → misoclib/mem/sdram/core/lasmicon/__init__.py
@@ -1,29 +1,29 @@
 from migen.fhdl.std import *
 
 from misoclib.mem.sdram.bus import dfi, lasmibus
-from misoclib.mem.sdram.lasmicon.refresher import *
-from misoclib.mem.sdram.lasmicon.bankmachine import *
-from misoclib.mem.sdram.lasmicon.multiplexer import *
+from misoclib.mem.sdram.core.lasmicon.refresher import *
+from misoclib.mem.sdram.core.lasmicon.bankmachine import *
+from misoclib.mem.sdram.core.lasmicon.multiplexer import *
 
 class LASMIcon(Module):
-	def __init__(self, phy_settings, geom_settings, timing_settings):
-		if phy_settings.memtype in ["SDR"]:
-			burst_length = phy_settings.nphases*1 # command multiplication*SDR
-		elif phy_settings.memtype in ["DDR", "LPDDR", "DDR2", "DDR3"]:
-			burst_length = phy_settings.nphases*2 # command multiplication*DDR
+	def __init__(self, phy, geom_settings, timing_settings):
+		if phy.settings.memtype in ["SDR"]:
+			burst_length = phy.settings.nphases*1 # command multiplication*SDR
+		elif phy.settings.memtype in ["DDR", "LPDDR", "DDR2", "DDR3"]:
+			burst_length = phy.settings.nphases*2 # command multiplication*DDR
 		address_align = log2_int(burst_length)
 
 		self.dfi = dfi.Interface(geom_settings.mux_a,
 			geom_settings.bank_a,
-			phy_settings.dfi_d,
-			phy_settings.nphases)
+			phy.settings.dfi_d,
+			phy.settings.nphases)
 		self.lasmic = lasmibus.Interface(
 			aw=geom_settings.row_a + geom_settings.col_a - address_align,
-			dw=phy_settings.dfi_d*phy_settings.nphases,
+			dw=phy.settings.dfi_d*phy.settings.nphases,
 			nbanks=2**geom_settings.bank_a,
 			req_queue_size=timing_settings.req_queue_size,
-			read_latency=phy_settings.read_latency+1,
-			write_latency=phy_settings.write_latency+1)
+			read_latency=phy.settings.read_latency+1,
+			write_latency=phy.settings.write_latency+1)
 		self.nrowbits = geom_settings.col_a - address_align
 
 		###
@@ -33,7 +33,7 @@ def __init__(self, phy_settings, geom_settings, timing_settings):
 		self.submodules.bank_machines = [BankMachine(geom_settings, timing_settings, address_align, i,
 				getattr(self.lasmic, "bank"+str(i)))
 			for i in range(2**geom_settings.bank_a)]
-		self.submodules.multiplexer = Multiplexer(phy_settings, geom_settings, timing_settings,
+		self.submodules.multiplexer = Multiplexer(phy, geom_settings, timing_settings,
 			self.bank_machines, self.refresher,
 			self.dfi, self.lasmic)
 

diff --git a/misoclib/mem/sdram/lasmicon/bankmachine.py → ...ib/mem/sdram/core/lasmicon/bankmachine.py b/misoclib/mem/sdram/lasmicon/bankmachine.py → ...ib/mem/sdram/core/lasmicon/bankmachine.py
@@ -4,7 +4,7 @@
 from migen.genlib.misc import optree
 from migen.genlib.fifo import SyncFIFO
 
-from misoclib.mem.sdram.lasmicon.multiplexer import *
+from misoclib.mem.sdram.core.lasmicon.multiplexer import *
 
 class _AddressSlicer:
 	def __init__(self, col_a, address_align):

diff --git a/misoclib/mem/sdram/lasmicon/crossbar.py → misoclib/mem/sdram/core/lasmicon/crossbar.py b/misoclib/mem/sdram/lasmicon/crossbar.py → misoclib/mem/sdram/core/lasmicon/crossbar.py
diff --git a/misoclib/mem/sdram/lasmicon/multiplexer.py → ...ib/mem/sdram/core/lasmicon/multiplexer.py b/misoclib/mem/sdram/lasmicon/multiplexer.py → ...ib/mem/sdram/core/lasmicon/multiplexer.py
@@ -4,7 +4,7 @@
 from migen.genlib.fsm import FSM, NextState
 from migen.bank.description import AutoCSR
 
-from misoclib.mem.sdram.lasmicon.perf import Bandwidth
+from misoclib.mem.sdram.core.lasmicon.perf import Bandwidth
 
 class CommandRequest:
 	def __init__(self, a, ba):
@@ -89,8 +89,8 @@ def stb_and(cmd, attr):
 			]
 
 class Multiplexer(Module, AutoCSR):
-	def __init__(self, phy_settings, geom_settings, timing_settings, bank_machines, refresher, dfi, lasmic):
-		assert(phy_settings.nphases == len(dfi.phases))
+	def __init__(self, phy, geom_settings, timing_settings, bank_machines, refresher, dfi, lasmic):
+		assert(phy.settings.nphases == len(dfi.phases))
 
 		# Command choosing
 		requests = [bm.cmd for bm in bank_machines]
@@ -100,7 +100,7 @@ def __init__(self, phy_settings, geom_settings, timing_settings, bank_machines,
 			choose_cmd.want_reads.eq(0),
 			choose_cmd.want_writes.eq(0)
 		]
-		if phy_settings.nphases == 1:
+		if phy.settings.nphases == 1:
 			self.comb += [
 				choose_cmd.want_cmds.eq(1),
 				choose_req.want_cmds.eq(1)
@@ -159,19 +159,19 @@ def anti_starvation(timeout):
 		fsm = FSM()
 		self.submodules += fsm
 
-		def steerer_sel(steerer, phy_settings, r_w_n):
+		def steerer_sel(steerer, phy, r_w_n):
 			r = []
-			for i in range(phy_settings.nphases):
+			for i in range(phy.settings.nphases):
 				s = steerer.sel[i].eq(STEER_NOP)
 				if r_w_n == "read":
-					if i == phy_settings.rdphase:
+					if i == phy.settings.rdphase:
 						s = steerer.sel[i].eq(STEER_REQ)
-					elif i == phy_settings.rdcmdphase:
+					elif i == phy.settings.rdcmdphase:
 						s = steerer.sel[i].eq(STEER_CMD)
 				elif r_w_n == "write":
-					if i == phy_settings.wrphase:
+					if i == phy.settings.wrphase:
 						s = steerer.sel[i].eq(STEER_REQ)
-					elif i == phy_settings.wrcmdphase:
+					elif i == phy.settings.wrcmdphase:
 						s = steerer.sel[i].eq(STEER_CMD)
 				else:
 					raise ValueError
@@ -183,7 +183,7 @@ def steerer_sel(steerer, phy_settings, r_w_n):
 			choose_req.want_reads.eq(1),
 			choose_cmd.cmd.ack.eq(1),
 			choose_req.cmd.ack.eq(1),
-			steerer_sel(steerer, phy_settings, "read"),
+			steerer_sel(steerer, phy, "read"),
 			If(write_available,
 				# TODO: switch only after several cycles of ~read_available?
 				If(~read_available | max_read_time, NextState("RTW"))
@@ -195,7 +195,7 @@ def steerer_sel(steerer, phy_settings, r_w_n):
 			choose_req.want_writes.eq(1),
 			choose_cmd.cmd.ack.eq(1),
 			choose_req.cmd.ack.eq(1),
-			steerer_sel(steerer, phy_settings, "write"),
+			steerer_sel(steerer, phy, "write"),
 			If(read_available,
 				If(~write_available | max_write_time, NextState("WTR"))
 			),
@@ -205,7 +205,7 @@ def steerer_sel(steerer, phy_settings, r_w_n):
 			steerer.sel[0].eq(STEER_REFRESH),
 			If(~refresher.req, NextState("READ"))
 		)
-		fsm.delayed_enter("RTW", "WRITE", phy_settings.read_latency-1) # FIXME: reduce this, actual limit is around (cl+1)/nphases
+		fsm.delayed_enter("RTW", "WRITE", phy.settings.read_latency-1) # FIXME: reduce this, actual limit is around (cl+1)/nphases
 		fsm.delayed_enter("WTR", "READ", timing_settings.tWTR-1)
 		# FIXME: workaround for zero-delay loop simulation problem with Icarus Verilog
 		fsm.finalize()

diff --git a/misoclib/mem/sdram/lasmicon/perf.py → misoclib/mem/sdram/core/lasmicon/perf.py b/misoclib/mem/sdram/lasmicon/perf.py → misoclib/mem/sdram/core/lasmicon/perf.py
diff --git a/misoclib/mem/sdram/lasmicon/refresher.py → ...clib/mem/sdram/core/lasmicon/refresher.py b/misoclib/mem/sdram/lasmicon/refresher.py → ...clib/mem/sdram/core/lasmicon/refresher.py
@@ -2,7 +2,7 @@
 from migen.genlib.misc import timeline
 from migen.genlib.fsm import FSM
 
-from misoclib.mem.sdram.lasmicon.multiplexer import *
+from misoclib.mem.sdram.core.lasmicon.multiplexer import *
 
 class Refresher(Module):
 	def __init__(self, a, ba, tRP, tREFI, tRFC):

diff --git a/misoclib/mem/sdram/minicon/__init__.py → misoclib/mem/sdram/core/minicon/__init__.py b/misoclib/mem/sdram/minicon/__init__.py → misoclib/mem/sdram/core/minicon/__init__.py
@@ -35,26 +35,26 @@ def col(self, address):
 			return Cat(Replicate(0, self.address_align), address[:split])
 
 class Minicon(Module):
-	def __init__(self, phy_settings, geom_settings, timing_settings):
-		if phy_settings.memtype in ["SDR"]:
-			burst_length = phy_settings.nphases*1 # command multiplication*SDR
-		elif phy_settings.memtype in ["DDR", "LPDDR", "DDR2", "DDR3"]:
-			burst_length = phy_settings.nphases*2 # command multiplication*DDR
+	def __init__(self, phy, geom_settings, timing_settings):
+		if phy.settings.memtype in ["SDR"]:
+			burst_length = phy.settings.nphases*1 # command multiplication*SDR
+		elif phy.settings.memtype in ["DDR", "LPDDR", "DDR2", "DDR3"]:
+			burst_length = phy.settings.nphases*2 # command multiplication*DDR
 		address_align = log2_int(burst_length)
 
 		nbanks = range(2**geom_settings.bank_a)
 		A10_ENABLED = 0
 		COLUMN      = 1
 		ROW         = 2
-		rdphase = phy_settings.rdphase
-		wrphase = phy_settings.wrphase
+		rdphase = phy.settings.rdphase
+		wrphase = phy.settings.wrphase
 
 		self.dfi = dfi = dfibus.Interface(geom_settings.mux_a,
 			geom_settings.bank_a,
-			phy_settings.dfi_d,
-			phy_settings.nphases)
+			phy.settings.dfi_d,
+			phy.settings.nphases)
 
-		self.bus = bus = wishbone.Interface(data_width=phy_settings.nphases*flen(dfi.phases[rdphase].rddata))
+		self.bus = bus = wishbone.Interface(data_width=phy.settings.nphases*flen(dfi.phases[rdphase].rddata))
 		slicer = _AddressSlicer(geom_settings.col_a, geom_settings.bank_a, geom_settings.row_a, address_align)
 		refresh_req = Signal()
 		refresh_ack = Signal()

diff --git a/misoclib/mem/sdram/phy/dfii.py b/misoclib/mem/sdram/phy/dfii.py
@@ -36,7 +36,9 @@ def __init__(self, phase):
 		self.sync += If(phase.rddata_valid, self._rddata.status.eq(phase.rddata))
 
 class DFIInjector(Module, AutoCSR):
-	def __init__(self, a, ba, d, nphases=1):
+	def __init__(self, phy, a, ba):
+		d = phy.settings.dfi_d
+		nphases = phy.settings.nphases
 		inti = dfi.Interface(a, ba, d, nphases)
 		self.slave = dfi.Interface(a, ba, d, nphases)
 		self.master = dfi.Interface(a, ba, d, nphases)

diff --git a/misoclib/mem/sdram/phy/gensdrphy.py b/misoclib/mem/sdram/phy/gensdrphy.py
@@ -34,7 +34,7 @@ def __init__(self, pads):
 		ba = flen(pads.ba)
 		d = flen(pads.dq)
 
-		self.phy_settings = sdram.PhySettings(
+		self.settings = sdram.PhySettings(
 			memtype="SDR",
 			dfi_d=d,
 			nphases=1,

diff --git a/misoclib/mem/sdram/phy/initsequence.py b/misoclib/mem/sdram/phy/initsequence.py
@@ -4,7 +4,7 @@ def get_sdram_phy_header(sdram_phy):
 	r = "#ifndef __GENERATED_SDRAM_PHY_H\n#define __GENERATED_SDRAM_PHY_H\n"
 	r += "#include <hw/common.h>\n#include <generated/csr.h>\n#include <hw/flags.h>\n\n"
 
-	nphases = sdram_phy.phy_settings.nphases
+	nphases = sdram_phy.settings.nphases
 	r += "#define DFII_NPHASES "+str(nphases)+"\n\n"
 
 	r += "static void cdelay(int i);\n"
@@ -14,45 +14,45 @@ def get_sdram_phy_header(sdram_phy):
 		r += """
 static void command_p{n}(int cmd)
 {{
-	dfii_pi{n}_command_write(cmd);
-	dfii_pi{n}_command_issue_write(1);
+	sdram_dfii_pi{n}_command_write(cmd);
+	sdram_dfii_pi{n}_command_issue_write(1);
 }}""".format(n=str(n))
 	r += "\n\n"
 
 	# rd/wr access macros
 	r += """
-#define dfii_pird_address_write(X) dfii_pi{rdphase}_address_write(X)
-#define dfii_piwr_address_write(X) dfii_pi{wrphase}_address_write(X)
+#define sdram_dfii_pird_address_write(X) sdram_dfii_pi{rdphase}_address_write(X)
+#define sdram_dfii_piwr_address_write(X) sdram_dfii_pi{wrphase}_address_write(X)
 
-#define dfii_pird_baddress_write(X) dfii_pi{rdphase}_baddress_write(X)
-#define dfii_piwr_baddress_write(X) dfii_pi{wrphase}_baddress_write(X)
+#define sdram_dfii_pird_baddress_write(X) sdram_dfii_pi{rdphase}_baddress_write(X)
+#define sdram_dfii_piwr_baddress_write(X) sdram_dfii_pi{wrphase}_baddress_write(X)
 
 #define command_prd(X) command_p{rdphase}(X)
 #define command_pwr(X) command_p{wrphase}(X)
-""".format(rdphase=str(sdram_phy.phy_settings.rdphase), wrphase=str(sdram_phy.phy_settings.wrphase))
+""".format(rdphase=str(sdram_phy.settings.rdphase), wrphase=str(sdram_phy.settings.wrphase))
 	r +="\n"
 
 	#
 	# sdrrd/sdrwr functions utilities
 	#
-	r += "#define DFII_PIX_DATA_SIZE CSR_DFII_PI0_WRDATA_SIZE\n"
-	dfii_pix_wrdata_addr = []
+	r += "#define DFII_PIX_DATA_SIZE CSR_SDRAM_DFII_PI0_WRDATA_SIZE\n"
+	sdram_dfii_pix_wrdata_addr = []
 	for n in range(nphases):
-		dfii_pix_wrdata_addr.append("CSR_DFII_PI{n}_WRDATA_ADDR".format(n=n))
+		sdram_dfii_pix_wrdata_addr.append("CSR_SDRAM_DFII_PI{n}_WRDATA_ADDR".format(n=n))
 	r += """
-const unsigned int dfii_pix_wrdata_addr[{n}] = {{
-	{dfii_pix_wrdata_addr}
+const unsigned int sdram_dfii_pix_wrdata_addr[{n}] = {{
+	{sdram_dfii_pix_wrdata_addr}
 }};
-""".format(n=nphases, dfii_pix_wrdata_addr=",\n\t".join(dfii_pix_wrdata_addr))
+""".format(n=nphases, sdram_dfii_pix_wrdata_addr=",\n\t".join(sdram_dfii_pix_wrdata_addr))
 
-	dfii_pix_rddata_addr = []
+	sdram_dfii_pix_rddata_addr = []
 	for n in range(nphases):
-		dfii_pix_rddata_addr.append("CSR_DFII_PI{n}_RDDATA_ADDR".format(n=n))
+		sdram_dfii_pix_rddata_addr.append("CSR_SDRAM_DFII_PI{n}_RDDATA_ADDR".format(n=n))
 	r += """
-const unsigned int dfii_pix_rddata_addr[{n}] = {{
-	{dfii_pix_rddata_addr}
+const unsigned int sdram_dfii_pix_rddata_addr[{n}] = {{
+	{sdram_dfii_pix_rddata_addr}
 }};
-""".format(n=nphases, dfii_pix_rddata_addr=",\n\t".join(dfii_pix_rddata_addr))
+""".format(n=nphases, sdram_dfii_pix_rddata_addr=",\n\t".join(sdram_dfii_pix_rddata_addr))
 	r +="\n"
 
 	# init sequence
@@ -64,10 +64,10 @@ def get_sdram_phy_header(sdram_phy):
 		"CKE"           : "DFII_CONTROL_CKE|DFII_CONTROL_ODT|DFII_CONTROL_RESET_N"
 	}
 
-	cl = sdram_phy.phy_settings.cl
+	cl = sdram_phy.settings.cl
 
-	if sdram_phy.phy_settings.memtype == "SDR":
-		bl = sdram_phy.phy_settings.nphases
+	if sdram_phy.settings.memtype == "SDR":
+		bl = sdram_phy.settings.nphases
 		mr = log2_int(bl) + (cl << 4)
 		reset_dll = 1 << 8
 
@@ -81,8 +81,8 @@ def get_sdram_phy_header(sdram_phy):
 			("Load Mode Register / CL={0:d}, BL={1:d}".format(cl, bl), mr, 0, cmds["MODE_REGISTER"], 200)
 		]
 
-	elif sdram_phy.phy_settings.memtype == "DDR":
-		bl = 2*sdram_phy.phy_settings.nphases
+	elif sdram_phy.settings.memtype == "DDR":
+		bl = 2*sdram_phy.settings.nphases
 		mr  = log2_int(bl) + (cl << 4)
 		emr = 0
 		reset_dll = 1 << 8
@@ -98,8 +98,8 @@ def get_sdram_phy_header(sdram_phy):
 			("Load Mode Register / CL={0:d}, BL={1:d}".format(cl, bl), mr, 0, cmds["MODE_REGISTER"], 200)
 		]
 
-	elif sdram_phy.phy_settings.memtype == "LPDDR":
-		bl = 2*sdram_phy.phy_settings.nphases
+	elif sdram_phy.settings.memtype == "LPDDR":
+		bl = 2*sdram_phy.settings.nphases
 		mr  = log2_int(bl) + (cl << 4)
 		emr = 0
 		reset_dll = 1 << 8
@@ -115,8 +115,8 @@ def get_sdram_phy_header(sdram_phy):
 			("Load Mode Register / CL={0:d}, BL={1:d}".format(cl, bl), mr, 0, cmds["MODE_REGISTER"], 200)
 		]
 
-	elif sdram_phy.phy_settings.memtype == "DDR2":
-		bl = 2*sdram_phy.phy_settings.nphases
+	elif sdram_phy.settings.memtype == "DDR2":
+		bl = 2*sdram_phy.settings.nphases
 		wr = 2
 		mr = log2_int(bl) + (cl << 4) + (wr << 9)
 		emr = 0
@@ -139,8 +139,8 @@ def get_sdram_phy_header(sdram_phy):
 			("Load Extended Mode Register / OCD Default", emr+ocd, 1, cmds["MODE_REGISTER"], 0),
 			("Load Extended Mode Register / OCD Exit", emr, 1, cmds["MODE_REGISTER"], 0),
 		]
-	elif sdram_phy.phy_settings.memtype == "DDR3":
-		bl = 2*sdram_phy.phy_settings.nphases
+	elif sdram_phy.settings.memtype == "DDR3":
+		bl = 2*sdram_phy.settings.nphases
 		if bl != 8:
 			raise NotImplementedError("DDR3 PHY header generator only supports BL of 8")
 
@@ -188,7 +188,7 @@ def format_mr2(cwl, rtt_wr):
 
 		mr0 = format_mr0(cl, 8, 1) # wr=8 FIXME: this should be ceiling(tWR/tCK)
 		mr1 = format_mr1(1, 1) # Output Drive Strength RZQ/7 (34 ohm) / Rtt RZQ/4 (60 ohm)
-		mr2 = format_mr2(sdram_phy.phy_settings.cwl, 2) # Rtt(WR) RZQ/4
+		mr2 = format_mr2(sdram_phy.settings.cwl, 2) # Rtt(WR) RZQ/4
 		mr3 = 0
 
 		init_sequence = [
@@ -204,15 +204,15 @@ def format_mr2(cwl, rtt_wr):
 		# the value of MR1 needs to be modified during write leveling
 		r += "#define DDR3_MR1 {}\n\n".format(mr1)
 	else:
-		raise NotImplementedError("Unsupported memory type: "+sdram_phy.phy_settings.memtype)
+		raise NotImplementedError("Unsupported memory type: "+sdram_phy.settings.memtype)
 
 	r += "static void init_sequence(void)\n{\n"
 	for comment, a, ba, cmd, delay in init_sequence:
 		r += "\t/* {0} */\n".format(comment)
-		r += "\tdfii_pi0_address_write({0:#x});\n".format(a)
-		r += "\tdfii_pi0_baddress_write({0:d});\n".format(ba)
+		r += "\tsdram_dfii_pi0_address_write({0:#x});\n".format(a)
+		r += "\tsdram_dfii_pi0_baddress_write({0:d});\n".format(ba)
 		if cmd[:12] == "DFII_CONTROL":
-			r += "\tdfii_control_write({0});\n".format(cmd)
+			r += "\tsdram_dfii_control_write({0});\n".format(cmd)
 		else:
 			r += "\tcommand_p0({0});\n".format(cmd)
 		if delay: