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  • 2 commits
  • 6 files changed
  • 1 contributor

Commits on Mar 2, 2015

  1. sdram: improve memtest by adding 2 different writes/reads

    doing only a write and read is not enough: if we reloaded a fpga with write that is not working after functional fpga, it would not trigger an error.
    enjoy-digital committed Mar 2, 2015
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    0980bec View commit details
  2. sdram: reintroduce dat_ack change (it was a small issue on wishbone w…

    …rites (sending data 1 clock cycle too late) that was not detected by memtest)
    enjoy-digital committed Mar 2, 2015
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    6b24562 View commit details
3 changes: 2 additions & 1 deletion misoclib/mem/sdram/bus/lasmibus.py
Original file line number Diff line number Diff line change
@@ -18,7 +18,8 @@ def __init__(self, aw, dw, nbanks, req_queue_size, read_latency, write_latency):
("we", 1, DIR_M_TO_S),
("stb", 1, DIR_M_TO_S),
("req_ack", 1, DIR_S_TO_M),
("dat_ack", 1, DIR_S_TO_M),
("dat_w_ack", 1, DIR_S_TO_M),
("dat_r_ack", 1, DIR_S_TO_M),
("lock", 1, DIR_S_TO_M)
]
if nbanks > 1:
19 changes: 3 additions & 16 deletions misoclib/mem/sdram/frontend/dma_lasmi.py
Original file line number Diff line number Diff line change
@@ -42,20 +42,13 @@ def __init__(self, lasmim, fifo_depth=None):
request_enable.eq(rsv_level != fifo_depth)
]

# data available
data_available = lasmim.dat_ack
for i in range(lasmim.read_latency):
new_data_available = Signal()
self.sync += new_data_available.eq(data_available)
data_available = new_data_available

# FIFO
fifo = SyncFIFO(lasmim.dw, fifo_depth)
self.submodules += fifo

self.comb += [
fifo.din.eq(lasmim.dat_r),
fifo.we.eq(data_available),
fifo.we.eq(lasmim.dat_r_ack),

self.data.stb.eq(fifo.readable),
fifo.re.eq(self.data.ack),
@@ -86,15 +79,9 @@ def __init__(self, lasmim, fifo_depth=None):
fifo.din.eq(self.address_data.d)
]

data_valid = lasmim.dat_ack
for i in range(lasmim.write_latency):
new_data_valid = Signal()
self.sync += new_data_valid.eq(data_valid),
data_valid = new_data_valid

self.comb += [
fifo.re.eq(data_valid),
If(data_valid,
If(lasmim.dat_w_ack,
fifo.re.eq(1),
lasmim.dat_we.eq(2**(lasmim.dw//8)-1),
lasmim.dat_w.eq(fifo.dout)
),
40 changes: 18 additions & 22 deletions misoclib/mem/sdram/frontend/wishbone2lasmi.py
Original file line number Diff line number Diff line change
@@ -105,8 +105,6 @@ def word_is_last(word):
fsm = FSM(reset_state="IDLE")
self.submodules += fsm

fsm.delayed_enter("EVICT_DATAD", "EVICT_DATA", lasmim.write_latency-1)
fsm.delayed_enter("REFILL_DATAD", "REFILL_DATA", lasmim.read_latency-1)

fsm.act("IDLE",
If(self.wishbone.cyc & self.wishbone.stb, NextState("TEST_HIT"))
@@ -132,18 +130,17 @@ def word_is_last(word):
fsm.act("EVICT_REQUEST",
lasmim.stb.eq(1),
lasmim.we.eq(1),
If(lasmim.req_ack, NextState("EVICT_WAIT_DATA_ACK"))
)
fsm.act("EVICT_WAIT_DATA_ACK",
If(lasmim.dat_ack, NextState("EVICT_DATAD"))
If(lasmim.req_ack, NextState("EVICT_DATA"))
)
fsm.act("EVICT_DATA",
write_to_lasmi.eq(1),
word_inc.eq(1),
If(word_is_last(word),
NextState("REFILL_WRTAG"),
).Else(
NextState("EVICT_REQUEST")
If(lasmim.dat_w_ack,
write_to_lasmi.eq(1),
word_inc.eq(1),
If(word_is_last(word),
NextState("REFILL_WRTAG"),
).Else(
NextState("EVICT_REQUEST")
)
)
)

@@ -155,17 +152,16 @@ def word_is_last(word):
)
fsm.act("REFILL_REQUEST",
lasmim.stb.eq(1),
If(lasmim.req_ack, NextState("REFILL_WAIT_DATA_ACK"))
)
fsm.act("REFILL_WAIT_DATA_ACK",
If(lasmim.dat_ack, NextState("REFILL_DATAD"))
If(lasmim.req_ack, NextState("REFILL_DATA"))
)
fsm.act("REFILL_DATA",
write_from_lasmi.eq(1),
word_inc.eq(1),
If(word_is_last(word),
NextState("TEST_HIT"),
).Else(
NextState("REFILL_REQUEST")
If(lasmim.dat_r_ack,
write_from_lasmi.eq(1),
word_inc.eq(1),
If(word_is_last(word),
NextState("TEST_HIT"),
).Else(
NextState("REFILL_REQUEST")
)
)
)
5 changes: 3 additions & 2 deletions misoclib/mem/sdram/lasmicon/bankmachine.py
Original file line number Diff line number Diff line change
@@ -41,7 +41,7 @@ def __init__(self, geom_settings, timing_settings, address_align, bankn, req):
self.req_fifo.we.eq(req.stb),
req.req_ack.eq(self.req_fifo.writable),

self.req_fifo.re.eq(req.dat_ack),
self.req_fifo.re.eq(req.dat_w_ack | req.dat_r_ack),
req.lock.eq(self.req_fifo.readable)
]
reqf = self.req_fifo.dout
@@ -100,7 +100,8 @@ def __init__(self, geom_settings, timing_settings, address_align, bankn, req):
If(hit,
# NB: write-to-read specification is enforced by multiplexer
self.cmd.stb.eq(1),
req.dat_ack.eq(self.cmd.ack),
req.dat_w_ack.eq(self.cmd.ack & reqf.we),
req.dat_r_ack.eq(self.cmd.ack & ~reqf.we),
self.cmd.is_read.eq(~reqf.we),
self.cmd.is_write.eq(reqf.we),
self.cmd.cas_n.eq(0),
27 changes: 23 additions & 4 deletions misoclib/mem/sdram/lasmicon/crossbar.py
Original file line number Diff line number Diff line change
@@ -50,7 +50,9 @@ def do_finalize(self):
else:
controller_selected = [1]*nmasters
master_req_acks = [0]*nmasters
master_dat_acks = [0]*nmasters
master_dat_w_acks = [0]*nmasters
master_dat_r_acks = [0]*nmasters

rrs = [roundrobin.RoundRobin(nmasters, roundrobin.SP_CE) for n in range(self._nbanks)]
self.submodules += rrs
for nb, rr in enumerate(rrs):
@@ -82,11 +84,28 @@ def do_finalize(self):
]
master_req_acks = [master_req_ack | ((rr.grant == nm) & bank_selected[nm] & bank.req_ack)
for nm, master_req_ack in enumerate(master_req_acks)]
master_dat_acks = [master_dat_ack | ((rr.grant == nm) & bank.dat_ack)
for nm, master_dat_ack in enumerate(master_dat_acks)]
master_dat_w_acks = [master_dat_w_ack | ((rr.grant == nm) & bank.dat_w_ack)
for nm, master_dat_w_ack in enumerate(master_dat_w_acks)]
master_dat_r_acks = [master_dat_r_ack | ((rr.grant == nm) & bank.dat_r_ack)
for nm, master_dat_r_ack in enumerate(master_dat_r_acks)]

for nm, master_dat_w_ack in enumerate(master_dat_w_acks):
for i in range(self._write_latency):
new_master_dat_w_ack = Signal()
self.sync += new_master_dat_w_ack.eq(master_dat_w_ack)
master_dat_w_ack = new_master_dat_w_ack
master_dat_w_acks[nm] = master_dat_w_ack

for nm, master_dat_r_ack in enumerate(master_dat_r_acks):
for i in range(self._read_latency):
new_master_dat_r_ack = Signal()
self.sync += new_master_dat_r_ack.eq(master_dat_r_ack)
master_dat_r_ack = new_master_dat_r_ack
master_dat_r_acks[nm] = master_dat_r_ack

self.comb += [master.req_ack.eq(master_req_ack) for master, master_req_ack in zip(self._masters, master_req_acks)]
self.comb += [master.dat_ack.eq(master_dat_ack) for master, master_dat_ack in zip(self._masters, master_dat_acks)]
self.comb += [master.dat_w_ack.eq(master_dat_w_ack) for master, master_dat_w_ack in zip(self._masters, master_dat_w_acks)]
self.comb += [master.dat_r_ack.eq(master_dat_r_ack) for master, master_dat_r_ack in zip(self._masters, master_dat_r_acks)]

# route data writes
controller_selected_wl = controller_selected
25 changes: 17 additions & 8 deletions software/bios/sdram.c
Original file line number Diff line number Diff line change
@@ -40,7 +40,7 @@ void sdrrow(char *_row)
{
char *c;
unsigned int row;

if(*_row == 0) {
dfii_pi0_address_write(0x0000);
dfii_pi0_baddress_write(0);
@@ -104,7 +104,7 @@ void sdrrd(char *startaddr, char *dq)
return;
}
}

dfii_pird_address_write(addr);
dfii_pird_baddress_write(0);
command_prd(DFII_COMMAND_CAS|DFII_COMMAND_CS|DFII_COMMAND_RDDATA);
@@ -185,7 +185,7 @@ void sdrwr(char *startaddr)
for(p=0;p<DFII_NPHASES;p++)
for(i=0;i<DFII_PIX_DATA_SIZE;i++)
MMPTR(dfii_pix_wrdata_addr[p]+4*i) = 0x10*p + i;

dfii_piwr_address_write(addr);
dfii_piwr_baddress_write(0);
command_pwr(DFII_COMMAND_CAS|DFII_COMMAND_WE|DFII_COMMAND_CS|DFII_COMMAND_WRDATA);
@@ -422,21 +422,30 @@ int sdrlevel(void)

#endif /* DDRPHY_BASE */

#define TEST_SIZE (4*1024*1024)
#define TEST_SIZE (2*1024*1024)

int memtest_silent(void)
{
volatile unsigned int *array = (unsigned int *)SDRAM_BASE;
int i;
unsigned int prv;
unsigned int error_cnt;


for(i=0;i<TEST_SIZE/4;i++) {
array[i] = 0x5A5A5A5A;
}
error_cnt = 0;
for(i=0;i<TEST_SIZE/4;i++) {
if(array[i] != 0x5A5A5A5A)
error_cnt++;
}

prv = 0;
for(i=0;i<TEST_SIZE/4;i++) {
prv = 1664525*prv + 1013904223;
array[i] = prv;
}

prv = 0;
error_cnt = 0;
for(i=0;i<TEST_SIZE/4;i++) {
@@ -464,7 +473,7 @@ int memtest(void)
int sdrinit(void)
{
printf("Initializing SDRAM...\n");

init_sequence();
#ifdef DDRPHY_BASE
if(!sdrlevel())
@@ -473,7 +482,7 @@ int sdrinit(void)
dfii_control_write(DFII_CONTROL_SEL);
if(!memtest())
return 0;

return 1;
}