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enjoy-digitalenjoy-digital
committedMar 1, 2015
lasmi: simplify usage for the user (it's the job of the controller to manage write/read latencies on acks)
·
0.120.1
1 parent f58394f commit 6d83a11

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3 files changed

+43
-25
lines changed

3 files changed

+43
-25
lines changed
 

Diff for: ‎misoclib/mem/sdram/bus/lasmibus.py

+30-10
Original file line numberDiff line numberDiff line change
@@ -14,12 +14,13 @@ def __init__(self, aw, dw, nbanks, req_queue_size, read_latency, write_latency):
1414
self.write_latency = write_latency
1515

1616
bank_layout = [
17-
("adr", aw, DIR_M_TO_S),
18-
("we", 1, DIR_M_TO_S),
19-
("stb", 1, DIR_M_TO_S),
20-
("req_ack", 1, DIR_S_TO_M),
21-
("dat_ack", 1, DIR_S_TO_M),
22-
("lock", 1, DIR_S_TO_M)
17+
("adr", aw, DIR_M_TO_S),
18+
("we", 1, DIR_M_TO_S),
19+
("stb", 1, DIR_M_TO_S),
20+
("req_ack", 1, DIR_S_TO_M),
21+
("dat_w_ack", 1, DIR_S_TO_M),
22+
("dat_r_ack", 1, DIR_S_TO_M),
23+
("lock", 1, DIR_S_TO_M)
2324
]
2425
if nbanks > 1:
2526
layout = [("bank"+str(i), bank_layout) for i in range(nbanks)]
@@ -77,7 +78,9 @@ def do_finalize(self):
7778
else:
7879
controller_selected = [1]*nmasters
7980
master_req_acks = [0]*nmasters
80-
master_dat_acks = [0]*nmasters
81+
master_dat_w_acks = [0]*nmasters
82+
master_dat_r_acks = [0]*nmasters
83+
8184
rrs = [roundrobin.RoundRobin(nmasters, roundrobin.SP_CE) for n in range(self._nbanks)]
8285
self.submodules += rrs
8386
for nb, rr in enumerate(rrs):
@@ -109,11 +112,28 @@ def do_finalize(self):
109112
]
110113
master_req_acks = [master_req_ack | ((rr.grant == nm) & bank_selected[nm] & bank.req_ack)
111114
for nm, master_req_ack in enumerate(master_req_acks)]
112-
master_dat_acks = [master_dat_ack | ((rr.grant == nm) & bank.dat_ack)
113-
for nm, master_dat_ack in enumerate(master_dat_acks)]
115+
master_dat_w_acks = [master_dat_w_ack | ((rr.grant == nm) & bank.dat_w_ack)
116+
for nm, master_dat_w_ack in enumerate(master_dat_w_acks)]
117+
master_dat_r_acks = [master_dat_r_ack | ((rr.grant == nm) & bank.dat_r_ack)
118+
for nm, master_dat_r_ack in enumerate(master_dat_r_acks)]
119+
120+
for nm, master_dat_w_ack in enumerate(master_dat_w_acks):
121+
for i in range(self._write_latency):
122+
new_master_dat_w_ack = Signal()
123+
self.sync += new_master_dat_w_ack.eq(master_dat_w_ack)
124+
master_dat_w_ack = new_master_dat_w_ack
125+
master_dat_w_acks[nm] = master_dat_w_ack
126+
127+
for nm, master_dat_r_ack in enumerate(master_dat_r_acks):
128+
for i in range(self._read_latency):
129+
new_master_dat_r_ack = Signal()
130+
self.sync += new_master_dat_r_ack.eq(master_dat_r_ack)
131+
master_dat_r_ack = new_master_dat_r_ack
132+
master_dat_r_acks[nm] = master_dat_r_ack
114133

115134
self.comb += [master.req_ack.eq(master_req_ack) for master, master_req_ack in zip(self._masters, master_req_acks)]
116-
self.comb += [master.dat_ack.eq(master_dat_ack) for master, master_dat_ack in zip(self._masters, master_dat_acks)]
135+
self.comb += [master.dat_w_ack.eq(master_dat_w_ack) for master, master_dat_w_ack in zip(self._masters, master_dat_w_acks)]
136+
self.comb += [master.dat_r_ack.eq(master_dat_r_ack) for master, master_dat_r_ack in zip(self._masters, master_dat_r_acks)]
117137

118138
# route data writes
119139
controller_selected_wl = controller_selected

Diff for: ‎misoclib/mem/sdram/bus/wishbone2lasmi.py

+10-13
Original file line numberDiff line numberDiff line change
@@ -105,8 +105,6 @@ def word_is_last(word):
105105
fsm = FSM(reset_state="IDLE")
106106
self.submodules += fsm
107107

108-
fsm.delayed_enter("EVICT_DATAD", "EVICT_DATA", lasmim.write_latency-1)
109-
fsm.delayed_enter("REFILL_DATAD", "REFILL_DATA", lasmim.read_latency-1)
110108

111109
fsm.act("IDLE",
112110
If(self.wishbone.cyc & self.wishbone.stb, NextState("TEST_HIT"))
@@ -135,7 +133,7 @@ def word_is_last(word):
135133
If(lasmim.req_ack, NextState("EVICT_WAIT_DATA_ACK"))
136134
)
137135
fsm.act("EVICT_WAIT_DATA_ACK",
138-
If(lasmim.dat_ack, NextState("EVICT_DATAD"))
136+
If(lasmim.dat_w_ack, NextState("EVICT_DATA"))
139137
)
140138
fsm.act("EVICT_DATA",
141139
write_to_lasmi.eq(1),
@@ -155,17 +153,16 @@ def word_is_last(word):
155153
)
156154
fsm.act("REFILL_REQUEST",
157155
lasmim.stb.eq(1),
158-
If(lasmim.req_ack, NextState("REFILL_WAIT_DATA_ACK"))
159-
)
160-
fsm.act("REFILL_WAIT_DATA_ACK",
161-
If(lasmim.dat_ack, NextState("REFILL_DATAD"))
156+
If(lasmim.req_ack, NextState("REFILL_DATA"))
162157
)
163158
fsm.act("REFILL_DATA",
164-
write_from_lasmi.eq(1),
165-
word_inc.eq(1),
166-
If(word_is_last(word),
167-
NextState("TEST_HIT"),
168-
).Else(
169-
NextState("REFILL_REQUEST")
159+
If(lasmim.dat_r_ack,
160+
write_from_lasmi.eq(1),
161+
word_inc.eq(1),
162+
If(word_is_last(word),
163+
NextState("TEST_HIT"),
164+
).Else(
165+
NextState("REFILL_REQUEST")
166+
)
170167
)
171168
)

Diff for: ‎misoclib/mem/sdram/lasmicon/bankmachine.py

+3-2
Original file line numberDiff line numberDiff line change
@@ -41,7 +41,7 @@ def __init__(self, geom_settings, timing_settings, address_align, bankn, req):
4141
self.req_fifo.we.eq(req.stb),
4242
req.req_ack.eq(self.req_fifo.writable),
4343

44-
self.req_fifo.re.eq(req.dat_ack),
44+
self.req_fifo.re.eq(req.dat_w_ack | req.dat_r_ack),
4545
req.lock.eq(self.req_fifo.readable)
4646
]
4747
reqf = self.req_fifo.dout
@@ -100,7 +100,8 @@ def __init__(self, geom_settings, timing_settings, address_align, bankn, req):
100100
If(hit,
101101
# NB: write-to-read specification is enforced by multiplexer
102102
self.cmd.stb.eq(1),
103-
req.dat_ack.eq(self.cmd.ack),
103+
req.dat_w_ack.eq(self.cmd.ack & reqf.we),
104+
req.dat_r_ack.eq(self.cmd.ack & ~reqf.we),
104105
self.cmd.is_read.eq(~reqf.we),
105106
self.cmd.is_write.eq(reqf.we),
106107
self.cmd.cas_n.eq(0),

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