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Commit c86dd3c

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author
Sebastien Bourdeauducq
committedSep 10, 2012
Define clock domains instead of passing extra clocks as regular signals
·
0.120.1
1 parent 5931c5e commit c86dd3c

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6 files changed

+29
-35
lines changed

6 files changed

+29
-35
lines changed
 

‎constraints.py

+1-1
Original file line numberDiff line numberDiff line change
@@ -15,7 +15,7 @@ def add_vec(signal, pins, iostandard="LVCMOS33", extra=""):
1515
add(crg0.videoin_rst_n, "W17")
1616
add(crg0.flash_rst_n, "P22", extra="SLEW = FAST | DRIVE = 8")
1717
add(crg0.trigger_reset, "AA4")
18-
add(crg0.phy_clk, "M20")
18+
add(crg0.eth_clk_pad, "M20")
1919
add(crg0.vga_clk_pad, "A11")
2020

2121
add_vec(norflash0.adr, ["L22", "L20", "K22", "K21", "J19", "H20", "F22",

‎milkymist/framebuffer/__init__.py

+1-6
Original file line numberDiff line numberDiff line change
@@ -162,7 +162,6 @@ class FIFO(Actor):
162162
def __init__(self):
163163
super().__init__(("dac", Sink, _dac_layout))
164164

165-
self.vga_clk = Signal()
166165
self.vga_hsync_n = Signal()
167166
self.vga_vsync_n = Signal()
168167
self.vga_r = Signal(BV(_bpc_dac))
@@ -178,7 +177,7 @@ def get_fragment(self):
178177
Instance.Output("data_out", BV(data_width)),
179178
Instance.Output("empty", BV(1)),
180179
Instance.Input("read_en", BV(1)),
181-
Instance.Input("clk_read", self.vga_clk),
180+
Instance.ClockPort("clk_read", "vga"),
182181

183182
Instance.Input("data_in", BV(data_width)),
184183
Instance.Output("full", BV(1)),
@@ -247,10 +246,6 @@ def __init__(self, address, asmiport, simulation=False):
247246
self.bank = csrgen.Bank(fi.actor.get_registers() + self._comp_actor.get_registers(),
248247
address=address)
249248

250-
# VGA clock input
251-
if not simulation:
252-
self.vga_clk = fifo.actor.vga_clk
253-
254249
# Pads
255250
self.vga_psave_n = Signal()
256251
if not simulation:

‎milkymist/m1crg/__init__.py

+10-6
Original file line numberDiff line numberDiff line change
@@ -8,6 +8,10 @@ def __init__(self, infreq, outfreq1x):
88
self.trigger_reset = Signal()
99

1010
self.cd_sys = ClockDomain("sys")
11+
self.cd_sys2x_270 = ClockDomain("sys2x_270")
12+
self.cd_sys4x_wr = ClockDomain("sys4x_wr")
13+
self.cd_sys4x_rd = ClockDomain("sys4x_rd")
14+
self.cd_vga = ClockDomain("vga")
1115

1216
ratio = Fraction(outfreq1x)/Fraction(infreq)
1317
in_period = float(Fraction(1000000000)/Fraction(infreq))
@@ -20,20 +24,20 @@ def __init__(self, infreq, outfreq1x):
2024
Instance.Input("trigger_reset", self.trigger_reset),
2125

2226
Instance.Output("sys_clk", self.cd_sys.clk),
23-
Instance.Output("sys_rst", self.cd_sys.rst)
27+
Instance.Output("sys_rst", self.cd_sys.rst),
28+
Instance.Output("clk2x_270", self.cd_sys2x_270.clk),
29+
Instance.Output("clk4x_wr", self.cd_sys4x_wr.clk),
30+
Instance.Output("clk4x_rd", self.cd_sys4x_rd.clk),
31+
Instance.Output("vga_clk", self.cd_vga.clk)
2432
]
2533

2634
for name in [
2735
"ac97_rst_n",
2836
"videoin_rst_n",
2937
"flash_rst_n",
30-
"clk2x_270",
31-
"clk4x_wr",
3238
"clk4x_wr_strb",
33-
"clk4x_rd",
3439
"clk4x_rd_strb",
35-
"phy_clk",
36-
"vga_clk",
40+
"eth_clk_pad",
3741
"vga_clk_pad"
3842
]:
3943
s = Signal(name=name)

‎milkymist/s6ddrphy/__init__.py

+4-4
Original file line numberDiff line numberDiff line change
@@ -7,13 +7,13 @@ def __init__(self, a, ba, d):
77
Instance.Parameter("NUM_AD", a),
88
Instance.Parameter("NUM_BA", ba),
99
Instance.Parameter("NUM_D", d),
10-
Instance.ClockPort("sys_clk")
10+
Instance.ClockPort("sys_clk"),
11+
Instance.ClockPort("clk2x_270", "sys2x_270"),
12+
Instance.ClockPort("clk4x_wr", "sys4x_wr"),
13+
Instance.ClockPort("clk4x_rd", "sys4x_rd")
1114
]
1215
for name, width, cl in [
13-
("clk2x_270", 1, Instance.Input),
14-
("clk4x_wr", 1, Instance.Input),
1516
("clk4x_wr_strb", 1, Instance.Input),
16-
("clk4x_rd", 1, Instance.Input),
1717
("clk4x_rd_strb", 1, Instance.Input),
1818

1919
("sd_clk_out_p", 1, Instance.Output),

‎top.py

+11-16
Original file line numberDiff line numberDiff line change
@@ -46,17 +46,6 @@ def ns(t, margin=True):
4646
write_time=16
4747
)
4848

49-
def ddrphy_clocking(crg, phy):
50-
names = [
51-
"clk2x_270",
52-
"clk4x_wr",
53-
"clk4x_wr_strb",
54-
"clk4x_rd",
55-
"clk4x_rd_strb"
56-
]
57-
comb = [getattr(phy, name).eq(getattr(crg, name)) for name in names]
58-
return Fragment(comb)
59-
6049
csr_macros = get_macros("common/csrbase.h")
6150
def csr_offset(name):
6251
base = int(csr_macros[name + "_BASE"], 0)
@@ -149,18 +138,24 @@ def get():
149138
#
150139
crg0 = m1crg.M1CRG(50*MHz, clk_freq)
151140

152-
vga_clocking = Fragment([
153-
fb0.vga_clk.eq(crg0.vga_clk)
141+
ddrphy_strobes = Fragment([
142+
ddrphy0.clk4x_wr_strb.eq(crg0.clk4x_wr_strb),
143+
ddrphy0.clk4x_rd_strb.eq(crg0.clk4x_rd_strb)
154144
])
155145
frag = autofragment.from_local() \
156146
+ interrupts \
157-
+ ddrphy_clocking(crg0, ddrphy0) \
158-
+ vga_clocking
147+
+ ddrphy_strobes
159148
cst = Constraints(crg0, norflash0, uart0, ddrphy0, minimac0, fb0)
160149
src_verilog, vns = verilog.convert(frag,
161150
cst.get_ios(),
162151
name="soc",
163-
clock_domains={"sys": crg0.cd_sys},
152+
clock_domains={
153+
"sys": crg0.cd_sys,
154+
"sys2x_270": crg0.cd_sys2x_270,
155+
"sys4x_wr": crg0.cd_sys4x_wr,
156+
"sys4x_rd": crg0.cd_sys4x_rd,
157+
"vga": crg0.cd_vga
158+
},
164159
return_ns=True)
165160
src_ucf = cst.get_ucf(vns)
166161
return (src_verilog, src_ucf)

‎verilog/m1crg/m1crg.v

+2-2
Original file line numberDiff line numberDiff line change
@@ -23,7 +23,7 @@ module m1crg #(
2323
output clk4x_rd_strb,
2424

2525
/* Ethernet PHY clock */
26-
output reg phy_clk, /* < unbuffered, to I/O */
26+
output reg eth_clk_pad, /* < unbuffered, to I/O */
2727

2828
/* VGA clock */
2929
output vga_clk, /* < buffered, to internal clock network */
@@ -193,7 +193,7 @@ BUFG bufg_x1(
193193

194194
/* Ethernet PHY */
195195
always @(posedge pllout4)
196-
phy_clk <= ~phy_clk;
196+
eth_clk_pad <= ~eth_clk_pad;
197197

198198
/* VGA clock */
199199
// TODO: hook up the reprogramming interface

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