Skip to content
Permalink

Comparing changes

Choose two branches to see what’s changed or to start a new pull request. If you need to, you can also or learn more about diff comparisons.

Open a pull request

Create a new pull request by comparing changes across two branches. If you need to, you can also . Learn more about diff comparisons here.
base repository: m-labs/misoc
Failed to load repositories. Confirm that selected base ref is valid, then try again.
Loading
base: 69a0c597adbe
Choose a base ref
...
head repository: m-labs/misoc
Failed to load repositories. Confirm that selected head ref is valid, then try again.
Loading
compare: ff29c86fe123
Choose a head ref
  • 3 commits
  • 3 files changed
  • 1 contributor

Commits on Mar 3, 2015

  1. README: 80 columns

    sbourdeauducq committed Mar 3, 2015
    Copy the full SHA
    2513833 View commit details
  2. spiflash: style

    sbourdeauducq committed Mar 3, 2015
    Copy the full SHA
    8e48502 View commit details
  3. Copy the full SHA
    ff29c86 View commit details
Showing with 17 additions and 14 deletions.
  1. +9 −6 README
  2. +2 −2 misoclib/mem/flash/spiflash/__init__.py
  3. +6 −6 misoclib/mem/litesata/example_designs/platforms/kc705.py
15 changes: 9 additions & 6 deletions README
Original file line number Diff line number Diff line change
@@ -69,10 +69,12 @@ modules.
make
make install

5. Compile and install GCC. Take gcc-core and gcc-g++ from GNU (version 4.5 or >=4.9).
5. Compile and install GCC. Take gcc-core and gcc-g++ from GNU
(version 4.5 or >=4.9).
rm -rf libstdc++-v3
mkdir build && cd build
../configure --target=lm32-elf --enable-languages="c,c++" --disable-libgcc --disable-libssp
../configure --target=lm32-elf --enable-languages="c,c++" --disable-libgcc \
--disable-libssp
make
make install

@@ -95,7 +97,8 @@ modules.
A simple target is provided to test MiSoC easily with your board:
Create your target with a clock and serial pins.
Build and test it: ./make.py -t simple -p your_platform all load-bitstream
If you don't have access to a FPGA board, you can also try MiSoC with Verilator:
If you don't have access to a FPGA board, you can also try MiSoC
with Verilator:
Download and install Verilator: http://www.veripool.org/
Test it: ./make.py -t simple -p sim build-bitstream

@@ -111,9 +114,9 @@ do them if possible:
* send us feedback and suggestions for improvements
* send us bug reports when something goes wrong
* send us the modifications and improvements you have done to MiSoC.
The use of "git format-patch" is recommended. If your submission is large and
complex and/or you are not sure how to proceed, feel free to discuss it on
the mailing list or IRC (#m-labs on Freenode) beforehand.
The use of "git format-patch" is recommended. If your submission is large
and complex and/or you are not sure how to proceed, feel free to discuss it
on the mailing list or IRC (#m-labs on Freenode) beforehand.

See LICENSE file for full copyright and license info.

4 changes: 2 additions & 2 deletions misoclib/mem/flash/spiflash/__init__.py
Original file line number Diff line number Diff line change
@@ -30,7 +30,7 @@ def __init__(self, pads, dummy=15, div=2, with_bitbang=True):
Supports multi-bit pseudo-parallel reads (aka Dual or Quad I/O Fast
Read). Only supports mode0 (cpol=0, cpha=0).
Optional supports software bitbanging (for write, erase, or other commands).
Optionally supports software bitbanging (for write, erase, or other commands).
"""
self.bus = bus = wishbone.Interface()
spi_width = flen(pads.dq)
@@ -39,7 +39,7 @@ def __init__(self, pads, dummy=15, div=2, with_bitbang=True):
self.miso = CSRStatus()
self.bitbang_en = CSRStorage()

##
###

cs_n = Signal(reset=1)
clk = Signal()
12 changes: 6 additions & 6 deletions misoclib/mem/litesata/example_designs/platforms/kc705.py
Original file line number Diff line number Diff line change
@@ -3,12 +3,12 @@

_sata_io = [
("sata", 0,
Subsignal("refclk_p", Pins("C8")),
Subsignal("refclk_n", Pins("C7")),
Subsignal("txp", Pins("D2")),
Subsignal("txn", Pins("D1")),
Subsignal("rxp", Pins("E4")),
Subsignal("rxn", Pins("E3")),
Subsignal("refclk_p", Pins("HPC:GBTCLK0_M2C_P")),
Subsignal("refclk_n", Pins("HPC:GBTCLK0_M2C_N")),
Subsignal("txp", Pins("HPC:DP0_C2M_P")),
Subsignal("txn", Pins("HPC:DP0_C2M_N")),
Subsignal("rxp", Pins("HPC:DP0_M2C_P")),
Subsignal("rxn", Pins("HPC:DP0_M2C_N")),
)
]