soc/target: remap RTIO to avoid conflict with spiflash and ddrphy in MiSoC

sbourdeauducq · sbourdeauducq · commit 346cca9e9045 · 2014-10-21T18:40:08.000+08:00
diff --git a/soc/targets/artiq.py b/soc/targets/artiq.py
@@ -41,7 +41,7 @@ def __init__(self, pad):
 
 class ARTIQMiniSoC(BaseSoC):
     csr_map = {
-        "rtio":            10
+        "rtio":            12
     }
     csr_map.update(BaseSoC.csr_map)
 

Original file line number	Diff line number	Diff line change
`@@ -41,7 +41,7 @@ def __init__(self, pad):`
`41`	`41`
`42`	`42`	`class ARTIQMiniSoC(BaseSoC):`
`43`	`43`	`csr_map = {`
`44`		`- "rtio": 10`
	`44`	`+ "rtio": 12`
`45`	`45`	`}`
`46`	`46`	`csr_map.update(BaseSoC.csr_map)`
`47`	`47`