soc/target: remap RTIO to avoid conflict with spiflash and ddrphy in …

…MiSoC
m-labs · Oct 21, 2014 · 346cca9 · 346cca9
1 parent 61a50ee
commit 346cca9
Showing 1 changed file with 1 addition and 1 deletion.
diff --git a/soc/targets/artiq.py b/soc/targets/artiq.py
@@ -41,7 +41,7 @@ def __init__(self, pad):
 
 class ARTIQMiniSoC(BaseSoC):
     csr_map = {
-        "rtio":            10
+        "rtio":            12
     }
     csr_map.update(BaseSoC.csr_map)