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soc/target: remap RTIO to avoid conflict with spiflash and ddrphy in …
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…MiSoC
sbourdeauducq committed Oct 21, 2014
1 parent 61a50ee commit 346cca9
Showing 1 changed file with 1 addition and 1 deletion.
2 changes: 1 addition & 1 deletion soc/targets/artiq.py
Original file line number Diff line number Diff line change
@@ -41,7 +41,7 @@ def __init__(self, pad):

class ARTIQMiniSoC(BaseSoC):
csr_map = {
"rtio": 10
"rtio": 12
}
csr_map.update(BaseSoC.csr_map)

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