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base repository: m-labs/misoc
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head repository: m-labs/misoc
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compare: 8c44c7249996
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  • 2 commits
  • 2 files changed
  • 1 contributor

Commits on Jul 15, 2013

  1. memtest: use actual values in TB

    Sebastien Bourdeauducq committed Jul 15, 2013
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    90fecb9 View commit details
  2. tb/lasmicon: add DF test

    Sebastien Bourdeauducq committed Jul 15, 2013
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    8c44c72 View commit details
Showing with 45 additions and 2 deletions.
  1. +2 −2 milkymist/memtest/__init__.py
  2. +43 −0 tb/lasmicon/lasmicon_df.py
4 changes: 2 additions & 2 deletions milkymist/memtest/__init__.py
Original file line number Diff line number Diff line change
@@ -39,11 +39,11 @@ def __init__(self, *args, **kwargs):
self.comb += self.lfsr.ce.eq(1)

def do_simulation(self, s):
print(s.rd(self.lfsr.o))
print("{0:032x}".format(s.rd(self.lfsr.o)))

def _sim_lfsr():
from migen.sim.generic import Simulator
tb = _LFSRTB(3, 4, [3, 2])
tb = _LFSRTB(128)
sim = Simulator(tb)
sim.run(20)

43 changes: 43 additions & 0 deletions tb/lasmicon/lasmicon_df.py
Original file line number Diff line number Diff line change
@@ -0,0 +1,43 @@
from migen.fhdl.std import *
from migen.bus import lasmibus
from migen.actorlib import dma_lasmi
from migen.sim.generic import Simulator, TopLevel, Proxy

from milkymist.lasmicon import *

from common import sdram_phy, sdram_geom, sdram_timing, DFILogger

class TB(Module):
def __init__(self):
self.submodules.ctler = LASMIcon(sdram_phy, sdram_geom, sdram_timing)
# FIXME: remove dummy master
self.submodules.xbar = lasmibus.Crossbar([self.ctler.lasmic], 2, self.ctler.nrowbits)
self.submodules.logger = DFILogger(self.ctler.dfi)
self.submodules.writer = dma_lasmi.Writer(self.xbar.masters[0])

self.comb += self.writer.address_data.stb.eq(1)
pl = self.writer.address_data.payload
pl.a.reset = 255
pl.d.reset = pl.a.reset*2
self.sync += If(self.writer.address_data.ack,
pl.a.eq(pl.a + 1),
pl.d.eq(pl.d + 2)
)
self.open_row = None

def do_simulation(self, s):
dfip = Proxy(s, self.ctler.dfi)
for p in dfip.phases:
if p.ras_n and not p.cas_n and not p.we_n: # write
d = dfip.phases[0].wrdata | (dfip.phases[1].wrdata << 64)
print(d)
if d != p.address//2 + p.bank*512 + self.open_row*2048:
print("**** ERROR ****")
elif not p.ras_n and p.cas_n and p.we_n: # activate
self.open_row = p.address

def main():
sim = Simulator(TB(), TopLevel("my.vcd"))
sim.run(3500)

main()