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base repository: m-labs/artiq
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  • 3 commits
  • 4 files changed
  • 2 contributors

Commits on Apr 15, 2015

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    30dffb6 View commit details
  2. generate MAILBOX_BASE with SoC and use it in runtime

    to avoid possible future mismatches between SoC/runtime, constants that can be easily generated from SoC should be defined this way.
    enjoy-digital authored and sbourdeauducq committed Apr 15, 2015
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    61a6506 View commit details
Showing with 47 additions and 1 deletion.
  1. +42 −0 artiq/gateware/rtio/phy/wishbone.py
  2. +2 −1 soc/runtime/mailbox.c
  3. +1 −0 soc/targets/artiq_kc705.py
  4. +2 −0 soc/targets/artiq_pipistrello.py
42 changes: 42 additions & 0 deletions artiq/gateware/rtio/phy/wishbone.py
Original file line number Diff line number Diff line change
@@ -0,0 +1,42 @@
from migen.fhdl.std import *

from artiq.gateware.rtio import rtlink


class RT2WB(Module):
def __init__(self, wb, address_width, o_latency=0, i_latency=0):
self.rtlink = rtlink.Interface(
rtlink.OInterface(
flen(wb.dat_w),
address_width + 1,
latency=o_latency,
suppress_nop=False),
rtlink.IInterface(
flen(wb.dat_r),
timestamped=False,
latency=i_latency)
)

# # #

active = Signal()
self.sync.rio += [
If(self.rtlink.o.stb,
active.eq(1),
wb.adr.eq(self.rtlink.o.address[:address_width]),
wb.we.eq(~self.rtlink.o.address[address_width]),
wb.dat_w.eq(self.rtlink.o.data),
wb.sel.eq(2**flen(wb.sel) - 1)
),
If(wb.ack,
active.eq(0)
)
]
self.comb += [
self.rtlink.o.busy.eq(active),
wb.cyc.eq(active),
wb.stb.eq(active),

self.i.stb.eq(wb.ack & ~wb.we),
self.i.data.eq(wb.dat_r)
]
3 changes: 2 additions & 1 deletion soc/runtime/mailbox.c
Original file line number Diff line number Diff line change
@@ -2,10 +2,11 @@
#include <system.h>
#include <spr-defs.h>
#include <hw/common.h>
#include <generated/mem.h>

#include "mailbox.h"

#define KERNELCPU_MAILBOX MMPTR(0xf0000000)
#define KERNELCPU_MAILBOX MMPTR(MAILBOX_BASE)

static unsigned int last_transmission;

1 change: 1 addition & 0 deletions soc/targets/artiq_kc705.py
Original file line number Diff line number Diff line change
@@ -125,6 +125,7 @@ def __init__(self, platform, *args, **kwargs):
self.submodules.mailbox = amp.Mailbox()
self.add_wb_slave(mem_decoder(self.mem_map["mailbox"]), self.mailbox.i1)
self.kernel_cpu.add_wb_slave(mem_decoder(self.mem_map["mailbox"]), self.mailbox.i2)
self.add_memory_region("mailbox", self.mem_map["mailbox"] + 0x80000000, 4)

rtio_csrs = self.rtio.get_kernel_csrs()
self.submodules.rtiowb = wbgen.Bank(rtio_csrs)
2 changes: 2 additions & 0 deletions soc/targets/artiq_pipistrello.py
Original file line number Diff line number Diff line change
@@ -155,6 +155,8 @@ def __init__(self, platform, *args, **kwargs):
self.mailbox.i1)
self.kernel_cpu.add_wb_slave(mem_decoder(self.mem_map["mailbox"]),
self.mailbox.i2)
self.add_memory_region("mailbox",
self.mem_map["mailbox"] + 0x80000000, 4)

rtio_csrs = self.rtio.get_kernel_csrs()
self.submodules.rtiowb = wbgen.Bank(rtio_csrs)