m-labs · Apr 15, 2015 · Apr 15, 2015 · Apr 15, 2015
Showing with 47 additions and 1 deletion.

+42 −0 artiq/gateware/rtio/phy/wishbone.py

+2 −1 soc/runtime/mailbox.c

+1 −0 soc/targets/artiq_kc705.py

+2 −0 soc/targets/artiq_pipistrello.py
diff --git a/artiq/gateware/rtio/phy/wishbone.py b/artiq/gateware/rtio/phy/wishbone.py
@@ -0,0 +1,42 @@
+from migen.fhdl.std import *
+
+from artiq.gateware.rtio import rtlink
+
+
+class RT2WB(Module):
+    def __init__(self, wb, address_width, o_latency=0, i_latency=0):
+        self.rtlink = rtlink.Interface(
+            rtlink.OInterface(
+                flen(wb.dat_w),
+                address_width + 1,
+                latency=o_latency,
+                suppress_nop=False),
+            rtlink.IInterface(
+                flen(wb.dat_r),
+                timestamped=False,
+                latency=i_latency)
+            )
+
+        # # #
+
+        active = Signal()
+        self.sync.rio += [
+            If(self.rtlink.o.stb,
+                active.eq(1),
+                wb.adr.eq(self.rtlink.o.address[:address_width]),
+                wb.we.eq(~self.rtlink.o.address[address_width]),
+                wb.dat_w.eq(self.rtlink.o.data),
+                wb.sel.eq(2**flen(wb.sel) - 1)
+            ),
+            If(wb.ack,
+                active.eq(0)
+            )
+        ]
+        self.comb += [
+            self.rtlink.o.busy.eq(active),
+            wb.cyc.eq(active),
+            wb.stb.eq(active),
+
+            self.i.stb.eq(wb.ack & ~wb.we),
+            self.i.data.eq(wb.dat_r)
+        ]
diff --git a/soc/runtime/mailbox.c b/soc/runtime/mailbox.c
@@ -2,10 +2,11 @@
 #include <system.h>
 #include <spr-defs.h>
 #include <hw/common.h>
+#include <generated/mem.h>
 
 #include "mailbox.h"
 
-#define KERNELCPU_MAILBOX MMPTR(0xf0000000)
+#define KERNELCPU_MAILBOX MMPTR(MAILBOX_BASE)
 
 static unsigned int last_transmission;
 

diff --git a/soc/targets/artiq_kc705.py b/soc/targets/artiq_kc705.py
@@ -125,6 +125,7 @@ def __init__(self, platform, *args, **kwargs):
         self.submodules.mailbox = amp.Mailbox()
         self.add_wb_slave(mem_decoder(self.mem_map["mailbox"]), self.mailbox.i1)
         self.kernel_cpu.add_wb_slave(mem_decoder(self.mem_map["mailbox"]), self.mailbox.i2)
+        self.add_memory_region("mailbox", self.mem_map["mailbox"] + 0x80000000, 4)
 
         rtio_csrs = self.rtio.get_kernel_csrs()
         self.submodules.rtiowb = wbgen.Bank(rtio_csrs)

diff --git a/soc/targets/artiq_pipistrello.py b/soc/targets/artiq_pipistrello.py
@@ -155,6 +155,8 @@ def __init__(self, platform, *args, **kwargs):
                           self.mailbox.i1)
         self.kernel_cpu.add_wb_slave(mem_decoder(self.mem_map["mailbox"]),
                                      self.mailbox.i2)
+        self.add_memory_region("mailbox",
+                               self.mem_map["mailbox"] + 0x80000000, 4)
 
         rtio_csrs = self.rtio.get_kernel_csrs()
         self.submodules.rtiowb = wbgen.Bank(rtio_csrs)