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base repository: m-labs/misoc
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compare: f32cdb1101af
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  • 2 commits
  • 5 files changed
  • 1 contributor

Commits on Apr 17, 2015

  1. soc/cpuif: add with_access_functions parameter

    When don't necessary need access functions in our csr.h (for example with an X86 CPU)
    enjoy-digital committed Apr 17, 2015
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    9666629 View commit details
  2. soc: add shadow_address parameter

    When don't necessary want to have shadow memories and be able to start CSR at address 0x00000000(for example with an X86 CPU)
    enjoy-digital committed Apr 17, 2015
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    f32cdb1 View commit details
Showing with 35 additions and 32 deletions.
  1. +6 −6 misoclib/soc/__init__.py
  2. +26 −23 misoclib/soc/cpuif.py
  3. +1 −1 targets/kc705.py
  4. +1 −1 targets/mlabs_video.py
  5. +1 −1 targets/simple.py
12 changes: 6 additions & 6 deletions misoclib/soc/__init__.py
Original file line number Diff line number Diff line change
@@ -29,10 +29,10 @@ class SoC(Module):
"timer0": 1,
}
mem_map = {
"rom": 0x00000000, # (shadow @0x80000000)
"sram": 0x10000000, # (shadow @0x90000000)
"main_ram": 0x40000000, # (shadow @0xc0000000)
"csr": 0x60000000, # (shadow @0xe0000000)
"rom": 0x00000000, # (default shadow @0x80000000)
"sram": 0x10000000, # (default shadow @0x90000000)
"main_ram": 0x40000000, # (default shadow @0xc0000000)
"csr": 0x60000000, # (default shadow @0xe0000000)
}
def __init__(self, platform, clk_freq,
cpu_type="lm32", cpu_reset_address=0x00000000,
@@ -190,9 +190,9 @@ def do_finalize(self):
data_width=self.csr_data_width, address_width=self.csr_address_width)
self.submodules.csrcon = csr.Interconnect(self.wishbone2csr.csr, self.csrbankarray.get_buses())
for name, csrs, mapaddr, rmap in self.csrbankarray.banks:
self.add_csr_region(name, self.mem_map["csr"]+0x80000000+0x800*mapaddr, self.csr_data_width, csrs)
self.add_csr_region(name, self.mem_map["csr"]+self.shadow_address+0x800*mapaddr, self.csr_data_width, csrs)
for name, memory, mapaddr, mmap in self.csrbankarray.srams:
self.add_csr_region(name + "_" + memory.name_override, self.mem_map["csr"]+0x80000000+0x800*mapaddr, self.csr_data_width, memory)
self.add_csr_region(name + "_" + memory.name_override, self.mem_map["csr"]+self.shadow_address+0x800*mapaddr, self.csr_data_width, memory)

# Interrupts
if hasattr(self.cpu_or_bridge, "interrupt"):
49 changes: 26 additions & 23 deletions misoclib/soc/cpuif.py
Original file line number Diff line number Diff line change
@@ -34,7 +34,7 @@ def get_mem_header(regions, flash_boot_address):
return r


def _get_rw_functions(reg_name, reg_base, nwords, busword, read_only):
def _get_rw_functions(reg_name, reg_base, nwords, busword, read_only, with_access_functions):
r = ""

r += "#define CSR_"+reg_name.upper()+"_ADDR "+hex(reg_base)+"\n"
@@ -52,30 +52,33 @@ def _get_rw_functions(reg_name, reg_base, nwords, busword, read_only):
else:
ctype = "unsigned char"

r += "static inline "+ctype+" "+reg_name+"_read(void) {\n"
if size > 1:
r += "\t"+ctype+" r = MMPTR("+hex(reg_base)+");\n"
for byte in range(1, nwords):
r += "\tr <<= "+str(busword)+";\n\tr |= MMPTR("+hex(reg_base+4*byte)+");\n"
r += "\treturn r;\n}\n"
else:
r += "\treturn MMPTR("+hex(reg_base)+");\n}\n"

if not read_only:
r += "static inline void "+reg_name+"_write("+ctype+" value) {\n"
for word in range(nwords):
shift = (nwords-word-1)*busword
if shift:
value_shifted = "value >> "+str(shift)
else:
value_shifted = "value"
r += "\tMMPTR("+hex(reg_base+4*word)+") = "+value_shifted+";\n"
r += "}\n"
if with_access_functions:
r += "static inline "+ctype+" "+reg_name+"_read(void) {\n"
if size > 1:
r += "\t"+ctype+" r = MMPTR("+hex(reg_base)+");\n"
for byte in range(1, nwords):
r += "\tr <<= "+str(busword)+";\n\tr |= MMPTR("+hex(reg_base+4*byte)+");\n"
r += "\treturn r;\n}\n"
else:
r += "\treturn MMPTR("+hex(reg_base)+");\n}\n"

if not read_only:
r += "static inline void "+reg_name+"_write("+ctype+" value) {\n"
for word in range(nwords):
shift = (nwords-word-1)*busword
if shift:
value_shifted = "value >> "+str(shift)
else:
value_shifted = "value"
r += "\tMMPTR("+hex(reg_base+4*word)+") = "+value_shifted+";\n"
r += "}\n"
return r


def get_csr_header(regions, constants):
r = "#ifndef __GENERATED_CSR_H\n#define __GENERATED_CSR_H\n#include <hw/common.h>\n"
def get_csr_header(regions, constants, with_access_functions=True):
r = "#ifndef __GENERATED_CSR_H\n#define __GENERATED_CSR_H\n"
if with_access_functions:
r += "#include <hw/common.h>\n"
for name, origin, busword, obj in regions:
if isinstance(obj, Memory):
r += "#define CSR_"+name.upper()+"_BASE "+hex(origin)+"\n"
@@ -84,7 +87,7 @@ def get_csr_header(regions, constants):
r += "#define CSR_"+name.upper()+"_BASE "+hex(origin)+"\n"
for csr in obj:
nr = (csr.size + busword - 1)//busword
r += _get_rw_functions(name + "_" + csr.name, origin, nr, busword, isinstance(csr, CSRStatus))
r += _get_rw_functions(name + "_" + csr.name, origin, nr, busword, isinstance(csr, CSRStatus), with_access_functions)
origin += 4*nr

r += "\n/* constants */\n"
2 changes: 1 addition & 1 deletion targets/kc705.py
Original file line number Diff line number Diff line change
@@ -125,6 +125,6 @@ def __init__(self, platform, **kwargs):
self.submodules.ethphy = LiteEthPHY(platform.request("eth_clocks"), platform.request("eth"))
self.submodules.ethmac = LiteEthMAC(phy=self.ethphy, dw=32, interface="wishbone")
self.add_wb_slave(mem_decoder(self.mem_map["ethmac"]), self.ethmac.bus)
self.add_memory_region("ethmac", self.mem_map["ethmac"]+0x80000000, 0x2000)
self.add_memory_region("ethmac", self.mem_map["ethmac"]+self.shadow_address, 0x2000)

default_subtarget = BaseSoC
2 changes: 1 addition & 1 deletion targets/mlabs_video.py
Original file line number Diff line number Diff line change
@@ -101,7 +101,7 @@ def __init__(self, platform, **kwargs):
platform.request("eth"))
self.submodules.ethmac = LiteEthMAC(phy=self.ethphy, dw=32, interface="wishbone")
self.add_wb_slave(mem_decoder(self.mem_map["ethmac"]), self.ethmac.bus)
self.add_memory_region("ethmac", self.mem_map["ethmac"]+0x80000000, 0x2000)
self.add_memory_region("ethmac", self.mem_map["ethmac"]+self.shadow_address, 0x2000)


def get_vga_dvi(platform):
2 changes: 1 addition & 1 deletion targets/simple.py
Original file line number Diff line number Diff line change
@@ -43,6 +43,6 @@ def __init__(self, platform, **kwargs):
interface="wishbone",
with_hw_preamble_crc=False)
self.add_wb_slave(mem_decoder(self.mem_map["ethmac"]), self.ethmac.bus)
self.add_memory_region("ethmac", self.mem_map["ethmac"]+0x80000000, 0x2000)
self.add_memory_region("ethmac", self.mem_map["ethmac"]+self.shadow_address, 0x2000)

default_subtarget = BaseSoC