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  • 3 commits
  • 57 files changed
  • 1 contributor

Commits on Apr 17, 2015

  1. add litepcie core

    enjoy-digital committed Apr 17, 2015
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Showing with 4,147 additions and 0 deletions.
  1. +3 −0 .gitmodules
  2. +1 −0 extcores/litepcie_phy_wrappers
  3. +28 −0 misoclib/com/litepcie/LICENSE
  4. +123 −0 misoclib/com/litepcie/README
  5. 0 misoclib/com/litepcie/__init__.py
  6. +74 −0 misoclib/com/litepcie/common.py
  7. +40 −0 misoclib/com/litepcie/core/__init__.py
  8. 0 misoclib/com/litepcie/core/irq/__init__.py
  9. +26 −0 misoclib/com/litepcie/core/irq/interrupt_controller.py
  10. 0 misoclib/com/litepcie/core/packet/__init__.py
  11. +117 −0 misoclib/com/litepcie/core/packet/common.py
  12. +170 −0 misoclib/com/litepcie/core/packet/depacketizer.py
  13. +197 −0 misoclib/com/litepcie/core/packet/packetizer.py
  14. 0 misoclib/com/litepcie/core/switch/__init__.py
  15. +25 −0 misoclib/com/litepcie/core/switch/arbiter.py
  16. +34 −0 misoclib/com/litepcie/core/switch/common.py
  17. +122 −0 misoclib/com/litepcie/core/switch/crossbar.py
  18. +40 −0 misoclib/com/litepcie/core/switch/dispatcher.py
  19. +175 −0 misoclib/com/litepcie/core/switch/request_controller.py
  20. 0 misoclib/com/litepcie/doc/.keep_me
  21. 0 misoclib/com/litepcie/example_designs/__init__.py
  22. 0 misoclib/com/litepcie/example_designs/build/.keep_me
  23. +148 −0 misoclib/com/litepcie/example_designs/make.py
  24. 0 misoclib/com/litepcie/example_designs/targets/__init__.py
  25. +98 −0 misoclib/com/litepcie/example_designs/targets/dma.py
  26. +36 −0 misoclib/com/litepcie/example_designs/test/make.py
  27. +14 −0 misoclib/com/litepcie/example_designs/test/test_regs.py
  28. 0 misoclib/com/litepcie/frontend/__init__.py
  29. 0 misoclib/com/litepcie/frontend/bridge/__init__.py
  30. +67 −0 misoclib/com/litepcie/frontend/bridge/wishbone.py
  31. +121 −0 misoclib/com/litepcie/frontend/dma/__init__.py
  32. +162 −0 misoclib/com/litepcie/frontend/dma/common.py
  33. +79 −0 misoclib/com/litepcie/frontend/dma/reader.py
  34. +88 −0 misoclib/com/litepcie/frontend/dma/writer.py
  35. +2 −0 misoclib/com/litepcie/litepcie-version.txt
  36. 0 misoclib/com/litepcie/phy/__init__.py
  37. +165 −0 misoclib/com/litepcie/phy/s7pciephy.py
  38. +16 −0 misoclib/com/litepcie/software/linux/kernel/Makefile
  39. +9 −0 misoclib/com/litepcie/software/linux/kernel/README
  40. +13 −0 misoclib/com/litepcie/software/linux/kernel/config.h
  41. +7 −0 misoclib/com/litepcie/software/linux/kernel/flags.h
  42. +7 −0 misoclib/com/litepcie/software/linux/kernel/init.sh
  43. +50 −0 misoclib/com/litepcie/software/linux/kernel/litepcie.h
  44. +639 −0 misoclib/com/litepcie/software/linux/kernel/main.c
  45. +19 −0 misoclib/com/litepcie/software/linux/user/Makefile
  46. +31 −0 misoclib/com/litepcie/software/linux/user/cutils.h
  47. +182 −0 misoclib/com/litepcie/software/linux/user/litepcie_lib.c
  48. +53 −0 misoclib/com/litepcie/software/linux/user/litepcie_lib.h
  49. +259 −0 misoclib/com/litepcie/software/linux/user/litepcie_util.c
  50. +10 −0 misoclib/com/litepcie/test/Makefile
  51. +36 −0 misoclib/com/litepcie/test/common.py
  52. +177 −0 misoclib/com/litepcie/test/dma_tb.py
  53. +142 −0 misoclib/com/litepcie/test/model/chipset.py
  54. +64 −0 misoclib/com/litepcie/test/model/host.py
  55. +144 −0 misoclib/com/litepcie/test/model/phy.py
  56. +94 −0 misoclib/com/litepcie/test/model/tlp.py
  57. +40 −0 misoclib/com/litepcie/test/wishbone_tb.py
3 changes: 3 additions & 0 deletions .gitmodules
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@@ -7,3 +7,6 @@
[submodule "software/compiler-rt"]
path = software/compiler-rt
url = http://llvm.org/git/compiler-rt.git
[submodule "extcores/litepcie_phy_wrappers"]
path = extcores/litepcie_phy_wrappers
url = https://github.com/enjoy-digital/litepcie_phy_wrappers
1 change: 1 addition & 0 deletions extcores/litepcie_phy_wrappers
Submodule litepcie_phy_wrappers added at 2e305d
28 changes: 28 additions & 0 deletions misoclib/com/litepcie/LICENSE
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@@ -0,0 +1,28 @@
Unless otherwise noted, LitePCIe is copyright (C) 2015 Florent Kermarrec.

Redistribution and use in source and binary forms, with or without modification,
are permitted provided that the following conditions are met:

1. Redistributions of source code must retain the above copyright notice, this
list of conditions and the following disclaimer.
2. Redistributions in binary form must reproduce the above copyright notice,
this list of conditions and the following disclaimer in the documentation
and/or other materials provided with the distribution.

THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR
ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.


Other authors retain ownership of their contributions. If a submission can
reasonably be considered independently copyrightable, it's yours and we
encourage you to claim it with appropriate copyright notices. This submission
then falls under the "otherwise noted" category. All submissions are strongly
encouraged to use the two-clause BSD license reproduced above.
123 changes: 123 additions & 0 deletions misoclib/com/litepcie/README
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@@ -0,0 +1,123 @@
__ _ __ ___ _________
/ / (_) /____ / _ \/ ___/ _/__
/ /__/ / __/ -_) ___/ /___/ // -_)
/____/_/\__/\__/_/ \___/___/\__/

Copyright 2015 / EnjoyDigital / M-Labs Ltd

A small footprint and configurable PCIe core
with MMAP interface and scatter-gather DMA
developed by EnjoyDigital

[> Doc
---------
XXX

[> Intro
---------
LitePCIe provides a small footprint and configurable PCIe gen1/2 core.

LitePCIe is part of MiSoC libraries whose aims are to lower entry level of
complex FPGA cores by providing simple, elegant and efficient implementations
ofcomponents used in today's SoC such as Ethernet, SATA, PCIe, SDRAM Controller...

The core uses simple and specific streaming buses and will provides in the future
adapters to use standardized AXI or Avalon-ST streaming buses.

Since Python is used to describe the HDL, the core is highly and easily
configurable.

LitePCIe uses technologies developed in partnership with M-Labs Ltd:
- Migen enables generating HDL with Python in an efficient way.
- MiSoC provides the basic blocks to build a powerful and small footprint SoC.

LitePCIe can be used as MiSoC library or can be integrated with your standard
design flow by generating the verilog rtl that you will use as a standard core.

[> Features
-----------
- 7-Series Artix7/Kintex7 PHY (up to PCIe Gen2 X2)
- Scatter-gather DMA
- Wishbone bridge
- Linux driver with DMA loopback demo and Sysfs


[> Possibles improvements
-------------------------
- add standardized interfaces (AXI, Avalon-ST)
- add support for PCIe Gen2 X4 and X8 on 7-Series
- clean up 7-Series wrappers
- add Altera/Lattice support
- ... See below Support and consulting :)

If you want to support these features, please contact us at florent [AT]
enjoy-digital.fr. You can also contact our partner on the public mailing list
devel [AT] lists.m-labs.hk.


[> Getting started
------------------
1. Install Python3 and your vendor's software

2. Obtain Migen and install it:
git clone https://github.com/m-labs/migen
cd migen
python3 setup.py install
cd ..

3. Obtain MiSoC:
git clone https://github.com/m-labs/misoc --recursive

4. Build and load PCIe DMA loopback design (only for KC705 for now):
go to misoclib/com/litepcie/example_designs/
run ./make.py all load-bitstream

5. Build and load Linux Driver:
go to misoclib/com/litepcie/software/linux/kernel
make all
./init.sh

5. Build and load Linux utilities:
go to misoclib/com/litepcie/software/linux/user
make all
./litepcie_util dma_loopback_test

[> Simulations:
Simulations are available in misoclib/com/litepcie/test:
- wishbone_tb
- dma_tb
To run a simulation, move to misoclib/com/litepcie/test/ and run:
make simulation_name

[> Tests :
A DMA loopback example with Wishbone over Sysfs is provided.
Please go to Getting Started section to see how to run the tests.

[> License
-----------
LitePCIe is released under the very permissive two-clause BSD license. Under
the terms of this license, you are authorized to use LiteEth for closed-source
proprietary designs.
Even though we do not require you to do so, those things are awesome, so please
do them if possible:
- tell us that you are using LitePCIe
- cite LitePCIe in publications related to research it has helped
- send us feedback and suggestions for improvements
- send us bug reports when something goes wrong
- send us the modifications and improvements you have done to LitePCIe.

[> Support and consulting
--------------------------
We love open-source hardware and like sharing our designs with others.

LitePCIe is mainly developed and maintained by EnjoyDigital.

If you would like to know more about LitePCIe or if you are already a happy
user and would like to extend it for your needs, EnjoyDigital can provide standard
commercial support as well as consulting services.

So feel free to contact us, we'd love to work with you! (and eventually shorten
the list of the possible improvements :)

[> Contact
E-mail: florent [AT] enjoy-digital.fr
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74 changes: 74 additions & 0 deletions misoclib/com/litepcie/common.py
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from migen.fhdl.std import *
from migen.genlib.record import *
from migen.flow.actor import *

KB = 1024
MB = 1024*KB
GB = 1024*MB


def get_bar_mask(size):
mask = 0
found = 0
for i in range(32):
if size%2:
found = 1
if found:
mask |= (1 << i)
size = size >> 1
return mask


def reverse_bytes(v):
return Cat(v[24:32], v[16:24], v[8:16], v[0:8])


def reverse_bits(v):
return Cat(v[3], v[2], v[1], v[0])


def phy_layout(dw):
layout = [
("dat", dw),
("be", dw//8)
]
return EndpointDescription(layout, packetized=True)


def request_layout(dw):
layout = [
("we", 1),
("adr", 32),
("len", 10),
("req_id", 16),
("tag", 8),
("dat", dw),
("channel", 8), # for routing
("user_id", 8) # for packet identification
]
return EndpointDescription(layout, packetized=True)


def completion_layout(dw):
layout = [
("adr", 32),
("len", 10),
("last", 1),
("req_id", 16),
("cmp_id", 16),
("err", 1),
("tag", 8),
("dat", dw),
("channel", 8), # for routing
("user_id", 8) # for packet identification
]
return EndpointDescription(layout, packetized=True)


def interrupt_layout():
return [("dat", 8)]


def dma_layout(dw):
layout = [("dat", dw)]
return EndpointDescription(layout, packetized=True)
40 changes: 40 additions & 0 deletions misoclib/com/litepcie/core/__init__.py
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from migen.fhdl.std import *
from migen.bank.description import *
from migen.genlib.record import *

from misoclib.com.litepcie.core.packet.depacketizer import Depacketizer
from misoclib.com.litepcie.core.packet.packetizer import Packetizer
from misoclib.com.litepcie.core.switch.crossbar import Crossbar


class Endpoint(Module):
def __init__(self, phy, max_pending_requests=4, with_reordering=False):
self.phy = phy
self.max_pending_requests = max_pending_requests

# # #

# TLP Packetizer / Depacketizer
depacketizer = Depacketizer(phy.dw, phy.bar0_mask)
packetizer = Packetizer(phy.dw)
self.submodules += depacketizer, packetizer
self.comb += [
phy.source.connect(depacketizer.sink),
packetizer.source.connect(phy.sink)
]

# Crossbar
self.crossbar = crossbar = Crossbar(phy.dw, max_pending_requests, with_reordering)
self.submodules += crossbar

# (Slave) HOST initiates the transactions
self.comb += [
Record.connect(depacketizer.req_source, crossbar.phy_slave.sink),
Record.connect(crossbar.phy_slave.source, packetizer.cmp_sink)
]

# (Master) FPGA initiates the transactions
self.comb += [
Record.connect(crossbar.phy_master.source, packetizer.req_sink),
Record.connect(depacketizer.cmp_source, crossbar.phy_master.sink)
]
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26 changes: 26 additions & 0 deletions misoclib/com/litepcie/core/irq/interrupt_controller.py
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from migen.fhdl.std import *
from migen.bank.description import *

from misoclib.com.litepcie.common import *


class InterruptController(Module, AutoCSR):
def __init__(self, n_irqs=32):
self.irqs = Signal(n_irqs)
self.source = Source(interrupt_layout())

self._enable = CSRStorage(n_irqs)
self._clear = CSR(n_irqs)
self._vector = CSRStatus(n_irqs)

# # #

enable = self._enable.storage
clear = Signal(n_irqs)
self.comb += If(self._clear.re, clear.eq(self._clear.r))

# memorize and clear irqs
vector = self._vector.status
self.sync += vector.eq(~clear & (vector | self.irqs))

self.comb += self.source.stb.eq((vector & enable) != 0)
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