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liteeth/phy/gmii_mii: add clock counter and use it in bios to select …
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…mode
enjoy-digital committed Apr 12, 2015

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1 parent 857bee8 commit 5153986
Showing 4 changed files with 43 additions and 1 deletion.
17 changes: 16 additions & 1 deletion misoclib/com/liteeth/phy/gmii_mii.py
Original file line number Diff line number Diff line change
@@ -1,10 +1,11 @@
from migen.genlib.io import DDROutput
from migen.flow.plumbing import Multiplexer, Demultiplexer
from migen.genlib.cdc import MultiReg

from misoclib.com.liteeth.common import *
from misoclib.com.liteeth.generic import *

from misoclib.com.liteeth.phy.gmii import LiteEthPHYGMIIMIICRG
from misoclib.com.liteeth.phy.gmii import LiteEthPHYGMIICRG
from misoclib.com.liteeth.phy.mii import LiteEthPHYMIITX, LiteEthPHYMIIRX
from misoclib.com.liteeth.phy.gmii import LiteEthPHYGMIITX, LiteEthPHYGMIIRX

@@ -67,13 +68,27 @@ def __init__(self, pads, mode):
Record.connect(mux.source, source)
]

class LiteEthGMIIMIIClockCounter(Module, AutoCSR):
def __init__(self):
self._reset = CSRStorage()
self._value = CSRStatus(32)
###
counter = RenameClockDomains(Counter(32), "eth_rx")
self.submodules += counter
self.comb += [
counter.reset.eq(self._reset.storage), #slow, don't need CDC
counter.ce.eq(1),
]
self.specials += MultiReg(counter.value, self._value.status)

class LiteEthPHYGMIIMII(Module, AutoCSR):
def __init__(self, clock_pads, pads, with_hw_init_reset=True):
self.dw = 8
self._mode = CSRStorage()
mode = self._mode.storage
# Note: we can use GMII CRG since it also handles tx clock pad used for MII
self.submodules.crg = LiteEthPHYGMIICRG(clock_pads, pads, with_hw_init_reset)
self.submodules.clock_counter = LiteEthGMIIMIIClockCounter()
self.submodules.tx = RenameClockDomains(LiteEthPHYGMIIMIITX(pads, mode), "eth_tx")
self.submodules.rx = RenameClockDomains(LiteEthPHYGMIIMIIRX(pads, mode), "eth_rx")
self.sink, self.source = self.tx.sink, self.rx.source
3 changes: 3 additions & 0 deletions software/bios/main.c
Original file line number Diff line number Diff line change
@@ -502,6 +502,9 @@ static void boot_sequence(void)
flashboot();
#endif
serialboot();
#ifdef CSR_ETHPHY_MODE_ADDR
ethmode();
#endif
#ifdef CSR_ETHMAC_BASE
netboot();
#endif
1 change: 1 addition & 0 deletions software/include/net/microudp.h
Original file line number Diff line number Diff line change
@@ -15,5 +15,6 @@ void microudp_set_callback(udp_callback callback);
void microudp_service(void);

void ethreset(void);
void ethmode(void);

#endif /* __MICROUDP_H */
23 changes: 23 additions & 0 deletions software/libnet/microudp.c
Original file line number Diff line number Diff line change
@@ -444,4 +444,27 @@ void ethreset(void)
busy_wait(2);
}

void ethmode(void)
{
ethphy_clock_counter_reset_write(1);
busy_wait(1);
ethphy_clock_counter_reset_write(0);
busy_wait(1);

printf("Ethernet phy mode: ");
/* if freq > 120 MHz, use GMII (5MHz margin)*/
if (ethphy_clock_counter_value_read() > 120000000/10) {

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@sbourdeauducq

sbourdeauducq Apr 12, 2015

Member

if(

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@enjoy-digital

enjoy-digital Apr 12, 2015

Author Contributor

Thanks, fixed.

ethphy_mode_write(0);
printf("GMII");
/* else use MII */
} else {
ethphy_mode_write(1);
printf("MII");
}
printf("\n");

ethphy_clock_counter_reset_write(1);
}

#endif

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