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base repository: m-labs/artiq
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head repository: m-labs/artiq
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compare: 485381fdbf4d
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  • 4 commits
  • 3 files changed
  • 1 contributor

Commits on Apr 16, 2015

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Showing with 34 additions and 17 deletions.
  1. +9 −9 artiq/gateware/rtio/core.py
  2. +2 −4 artiq/gateware/rtio/phy/wishbone.py
  3. +23 −4 artiq/gateware/rtio/rtlink.py
18 changes: 9 additions & 9 deletions artiq/gateware/rtio/core.py
Original file line number Diff line number Diff line change
@@ -268,15 +268,18 @@ def __init__(self, chan_sel_width,
self.reset = CSRStorage(reset=1)
self.chan_sel = CSRStorage(chan_sel_width)

self.o_data = CSRStorage(data_width)
self.o_address = CSRStorage(address_width)
if data_width:
self.o_data = CSRStorage(data_width)
if address_width:
self.o_address = CSRStorage(address_width)
self.o_timestamp = CSRStorage(full_ts_width)
self.o_we = CSR()
self.o_status = CSRStatus(3)
self.o_underflow_reset = CSR()
self.o_sequence_error_reset = CSR()

self.i_data = CSRStatus(data_width)
if data_width:
self.i_data = CSRStatus(data_width)
self.i_timestamp = CSRStatus(full_ts_width)
self.i_re = CSR()
self.i_status = CSRStatus(2)
@@ -299,8 +302,7 @@ def __init__(self, channels, clk_freq, counter_width=63,
# CSRs
self.csrs = _CSRs()
self.kcsrs = _KernelCSRs(bits_for(len(channels)-1),
max(data_width, 1),
max(address_width, 1),
data_width, address_width,
counter_width + fine_ts_width)

# Clocking/Reset
@@ -316,9 +318,6 @@ def __init__(self, channels, clk_freq, counter_width=63,
self.specials += AsyncResetSynchronizer(self.cd_rio,
self.kcsrs.reset.storage)

# Latency compensation
# TODO

# Managers
self.submodules.counter = _RTIOCounter(counter_width)

@@ -391,8 +390,9 @@ def __init__(self, channels, clk_freq, counter_width=63,
i_datas.append(0)
i_timestamps.append(0)
i_statuses.append(0)
if data_width:
self.comb += self.kcsrs.i_data.status.eq(Array(i_datas)[sel])
self.comb += [
self.kcsrs.i_data.status.eq(Array(i_datas)[sel]),
self.kcsrs.i_timestamp.status.eq(Array(i_timestamps)[sel]),
self.kcsrs.o_status.status.eq(Array(o_statuses)[sel]),
self.kcsrs.i_status.status.eq(Array(i_statuses)[sel])
6 changes: 2 additions & 4 deletions artiq/gateware/rtio/phy/wishbone.py
Original file line number Diff line number Diff line change
@@ -4,17 +4,15 @@


class RT2WB(Module):
def __init__(self, wb, address_width, o_latency=0, i_latency=0):
def __init__(self, wb, address_width):
self.rtlink = rtlink.Interface(
rtlink.OInterface(
flen(wb.dat_w),
address_width + 1,
latency=o_latency,
suppress_nop=False),
rtlink.IInterface(
flen(wb.dat_r),
timestamped=False,
latency=i_latency)
timestamped=False)
)

# # #
27 changes: 23 additions & 4 deletions artiq/gateware/rtio/rtlink.py
Original file line number Diff line number Diff line change
@@ -3,7 +3,7 @@

class OInterface:
def __init__(self, data_width, address_width=0,
fine_ts_width=0, latency=1, suppress_nop=True):
fine_ts_width=0, suppress_nop=True):
self.stb = Signal()
self.busy = Signal()

@@ -14,30 +14,49 @@ def __init__(self, data_width, address_width=0,
if fine_ts_width:
self.fine_ts = Signal(fine_ts_width)

self.latency = latency
self.suppress_nop = suppress_nop

@classmethod
def like(cls, other):
return cls(get_data_width(other),
get_address_width(other),
get_fine_ts_width(other),
other.suppress_nop)


class IInterface:
def __init__(self, data_width,
timestamped=True, fine_ts_width=0, latency=2):
timestamped=True, fine_ts_width=0):
self.stb = Signal()

if data_width:
self.data = Signal(data_width)
if fine_ts_width:
self.fine_ts = Signal(fine_ts_width)

self.latency = latency
self.timestamped = timestamped
assert(not fine_ts_width or timestamped)

@classmethod
def like(cls, other):
return cls(get_data_width(other),
other.timestamped,
get_fine_ts_width(other))


class Interface:
def __init__(self, o, i=None):
self.o = o
self.i = i

@classmethod
def like(cls, other):
if self.i is None:
return cls(OInterface.like(self.o))
else:
return cls(OInterface.like(self.o),
IInterface.like(self.i))


def _get_or_zero(interface, attr):
if isinstance(interface, Interface):