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liteeth/phy/gmii: fix clock generation for mii mode (clock_pads.tx is…
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… an input)
enjoy-digital committed Apr 12, 2015

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1 parent 3710afe commit afa9b88
Showing 2 changed files with 15 additions and 7 deletions.
20 changes: 14 additions & 6 deletions misoclib/com/liteeth/phy/gmii.py
Original file line number Diff line number Diff line change
@@ -40,16 +40,24 @@ def __init__(self, pads):
self.comb += source.eop.eq(eop)

class LiteEthPHYGMIICRG(Module, AutoCSR):
def __init__(self, clock_pads, pads, with_hw_init_reset):
def __init__(self, clock_pads, pads, with_hw_init_reset, mii_mode=0):
self._reset = CSRStorage()
###
self.clock_domains.cd_eth_rx = ClockDomain()
self.clock_domains.cd_eth_tx = ClockDomain()
self.specials += DDROutput(1, 0, clock_pads.gtx, ClockSignal("eth_tx"))
self.comb += [
self.cd_eth_rx.clk.eq(clock_pads.rx), # Let the synthesis tool insert
self.cd_eth_tx.clk.eq(self.cd_eth_rx.clk) # the appropriate clock buffer
]

# RX : Let the synthesis tool insert the appropriate clock buffer
self.comb += self.cd_eth_rx.clk.eq(clock_pads.rx)

# TX : GMII: Drive clock_pads.gtx, clock_pads.tx unused
# MII: Use PHY clock_pads.tx as eth_tx_clk, do not drive clock_pads.gtx
self.specials += DDROutput(1, mii_mode, clock_pads.gtx, ClockSignal("eth_tx"))
# XXX Xilinx specific, replace BUFGMUX with a generic clock buffer?
self.specials += Instance("BUFGMUX",
i_I0=self.cd_eth_rx.clk,
i_I1=clock_pads.tx,
i_S=mii_mode,
o_O=self.cd_eth_tx.clk)

if with_hw_init_reset:
reset = Signal()
2 changes: 1 addition & 1 deletion misoclib/com/liteeth/phy/gmii_mii.py
Original file line number Diff line number Diff line change
@@ -94,7 +94,7 @@ def __init__(self, clock_pads, pads, with_hw_init_reset=True):
self._mode = CSRStorage()
mode = self._mode.storage
# Note: we can use GMII CRG since it also handles tx clock pad used for MII
self.submodules.crg = LiteEthPHYGMIICRG(clock_pads, pads, with_hw_init_reset)
self.submodules.crg = LiteEthPHYGMIICRG(clock_pads, pads, with_hw_init_reset, mode==modes["MII"])
self.submodules.clock_counter = LiteEthGMIIMIIClockCounter()
self.submodules.tx = RenameClockDomains(LiteEthPHYGMIIMIITX(pads, mode), "eth_tx")
self.submodules.rx = RenameClockDomains(LiteEthPHYGMIIMIIRX(pads, mode), "eth_rx")

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