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base repository: m-labs/misoc
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head repository: m-labs/misoc
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compare: 8e639160e3a8
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  • 2 commits
  • 3 files changed
  • 1 contributor

Commits on Apr 12, 2015

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    0c27708 View commit details
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    8e63916 View commit details
Showing with 25 additions and 10 deletions.
  1. +6 −2 misoclib/com/liteeth/phy/gmii.py
  2. +13 −6 misoclib/com/liteeth/phy/gmii_mii.py
  3. +6 −2 misoclib/com/liteeth/phy/mii.py
8 changes: 6 additions & 2 deletions misoclib/com/liteeth/phy/gmii.py
Original file line number Diff line number Diff line change
@@ -4,15 +4,19 @@
from misoclib.com.liteeth.generic import *

class LiteEthPHYGMIITX(Module):
def __init__(self, pads):
def __init__(self, pads, pads_register):
self.sink = sink = Sink(eth_phy_description(8))
###
if hasattr(pads, "tx_er"):
self.sync += pads.tx_er.eq(0)
self.sync += [
pads_eq = [
pads.tx_en.eq(sink.stb),
pads.tx_data.eq(sink.data)
]
if pads_register:
self.sync += pads_eq
else:
self.comb += pads_eq
self.comb += sink.ack.eq(1)

class LiteEthPHYGMIIRX(Module):
19 changes: 13 additions & 6 deletions misoclib/com/liteeth/phy/gmii_mii.py
Original file line number Diff line number Diff line change
@@ -14,18 +14,19 @@
"MII" : 1
}

tx_pads_layout = [("tx_er", 1), ("tx_en", 1), ("tx_data", 8)]
rx_pads_layout = [("rx_er", 1), ("dv", 1), ("rx_data", 8)]

class LiteEthPHYGMIIMIITX(Module):
def __init__(self, pads, mode):
self.sink = sink = Sink(eth_phy_description(8))
###
tx_pads_layout = [("tx_er", 1), ("tx_en", 1), ("tx_data", 8)]

gmii_tx_pads = Record(tx_pads_layout)
gmii_tx = LiteEthPHYGMIITX(gmii_tx_pads)
gmii_tx = LiteEthPHYGMIITX(gmii_tx_pads, pads_register=False)
self.submodules += gmii_tx

mii_tx_pads = Record(tx_pads_layout)
mii_tx = LiteEthPHYMIITX(mii_tx_pads)
mii_tx = LiteEthPHYMIITX(mii_tx_pads, pads_register=False)
self.submodules += mii_tx

demux = Demultiplexer(eth_phy_description(8), 2)
@@ -53,10 +54,16 @@ class LiteEthPHYGMIIMIIRX(Module):
def __init__(self, pads, mode):
self.source = source = Source(eth_phy_description(8))
###
gmii_rx = LiteEthPHYGMIIRX(pads)
pads_d = Record(rx_pads_layout)
self.sync += [
pads_d.dv.eq(pads.dv),
pads_d.rx_data.eq(pads.rx_data)
]

gmii_rx = LiteEthPHYGMIIRX(pads_d)
self.submodules += gmii_rx

mii_rx = LiteEthPHYMIIRX(pads)
mii_rx = LiteEthPHYMIIRX(pads_d)
self.submodules += mii_rx

mux = Multiplexer(eth_phy_description(8), 2)
8 changes: 6 additions & 2 deletions misoclib/com/liteeth/phy/mii.py
Original file line number Diff line number Diff line change
@@ -6,7 +6,7 @@ def converter_description(dw):
return EndpointDescription(payload_layout, packetized=True)

class LiteEthPHYMIITX(Module):
def __init__(self, pads):
def __init__(self, pads, pads_register=True):
self.sink = sink = Sink(eth_phy_description(8))
###
if hasattr(pads, "tx_er"):
@@ -19,10 +19,14 @@ def __init__(self, pads):
sink.ack.eq(converter.sink.ack),
converter.source.ack.eq(1)
]
self.sync += [
pads_eq = [
pads.tx_en.eq(converter.source.stb),
pads.tx_data.eq(converter.source.data)
]
if pads_register:
self.sync += pads_eq
else:
self.comb += pads_eq

class LiteEthPHYMIIRX(Module):
def __init__(self, pads):