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coredevice,runtime: put ref_period into the ddb
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sbourdeauducq committed Apr 16, 2015
1 parent 485381f commit 546996f
Showing 10 changed files with 14 additions and 60 deletions.
9 changes: 1 addition & 8 deletions artiq/coredevice/comm_generic.py
Original file line number Diff line number Diff line change
@@ -108,12 +108,7 @@ def get_runtime_env(self):
if runtime_id != "AROR":
raise UnsupportedDevice("Unsupported runtime ID: {}"
.format(runtime_id))
ref_freq_i, ref_freq_fn, ref_freq_fd = struct.unpack(
">lBB", self._read(6))
ref_freq = (ref_freq_i + Fraction(ref_freq_fn, ref_freq_fd))*units.Hz
ref_period = 1/ref_freq
logger.debug("environment ref_period: %s", ref_period)
return Environment(ref_period)
return Environment()

def switch_clock(self, external):
self._write(struct.pack(
@@ -140,8 +135,6 @@ def run(self, kname):
self._write(struct.pack(">B", ord(c)))
logger.debug("running kernel: %s", kname)



def _receive_rpc_values(self):
r = []
while True:
12 changes: 4 additions & 8 deletions artiq/coredevice/core.py
Original file line number Diff line number Diff line change
@@ -47,19 +47,15 @@ def _no_debug_unparse(label, node):
class Core(AutoDB):
class DBKeys:
comm = Device()
external_clock = Parameter(None)
ref_period = Argument()
external_clock = Argument(False)

def build(self):
self.runtime_env = self.comm.get_runtime_env()
self.core = self
self.comm.core = self

if self.external_clock is None:
self.ref_period = self.runtime_env.internal_ref_period
self.comm.switch_clock(False)
else:
self.ref_period = 1/self.external_clock
self.comm.switch_clock(True)

self.comm.switch_clock(self.external_clock)
self.initial_time = int64(self.runtime_env.warmup_time/self.ref_period)

def transform_stack(self, func_def, rpc_map, exception_map,
6 changes: 2 additions & 4 deletions artiq/coredevice/runtime.py
Original file line number Diff line number Diff line change
@@ -190,9 +190,8 @@ def _debug_dump_obj(obj):


class Environment(LinkInterface):
def __init__(self, internal_ref_period):
def __init__(self):
self.cpu_type = "or1k"
self.internal_ref_period = internal_ref_period
# allow 1ms for all initial DDS programming
self.warmup_time = 1*units.ms

@@ -203,5 +202,4 @@ def emit_object(self):
return obj

def __repr__(self):
return "<Environment {} {}>".format(self.cpu_type,
str(1/self.ref_period))
return "<Environment {}>".format(self.cpu_type)
23 changes: 0 additions & 23 deletions artiq/gateware/rtio/core.py
Original file line number Diff line number Diff line change
@@ -1,5 +1,3 @@
from fractions import Fraction

from migen.fhdl.std import *
from migen.bank.description import *
from migen.genlib.misc import optree
@@ -255,13 +253,6 @@ def __init__(self, interface, ofifo_depth=64, ififo_depth=64):
self.ififo_depth = ififo_depth


class _CSRs(AutoCSR):
def __init__(self):
self.frequency_i = CSRStatus(32)
self.frequency_fn = CSRStatus(8)
self.frequency_fd = CSRStatus(8)


class _KernelCSRs(AutoCSR):
def __init__(self, chan_sel_width,
data_width, address_width, full_ts_width):
@@ -300,7 +291,6 @@ def __init__(self, channels, clk_freq, counter_width=63,
for c in channels)

# CSRs
self.csrs = _CSRs()
self.kcsrs = _KernelCSRs(bits_for(len(channels)-1),
data_width, address_width,
counter_width + fine_ts_width)
@@ -405,18 +395,5 @@ def __init__(self, channels, clk_freq, counter_width=63,
<< fine_ts_width)
)

# Frequency CSRs
clk_freq = Fraction(clk_freq).limit_denominator(255)
clk_freq_i = int(clk_freq)
clk_freq_f = clk_freq - clk_freq_i
self.comb += [
self.csrs.frequency_i.status.eq(clk_freq_i),
self.csrs.frequency_fn.status.eq(clk_freq_f.numerator),
self.csrs.frequency_fd.status.eq(clk_freq_f.denominator)
]

def get_csrs(self):
return self.csrs.get_csrs()

def get_kernel_csrs(self):
return self.kcsrs.get_csrs()
2 changes: 1 addition & 1 deletion benchmarks/ddb.pyon
Original file line number Diff line number Diff line change
@@ -9,7 +9,7 @@
"type": "local",
"module": "artiq.coredevice.core",
"class": "Core",
"arguments": {}
"arguments": {"ref_period": Quantity(Fraction(8, 1000000000), "s")}
},

"pmt0": {
2 changes: 1 addition & 1 deletion examples/master/ddb.pyon
Original file line number Diff line number Diff line change
@@ -9,7 +9,7 @@
"type": "local",
"module": "artiq.coredevice.core",
"class": "Core",
"arguments": {}
"arguments": {"ref_period": Quantity(Fraction(8, 1000000000), "s")}
},

"pmt0": {
10 changes: 0 additions & 10 deletions soc/runtime/comm_serial.c
Original file line number Diff line number Diff line change
@@ -178,16 +178,6 @@ void comm_serve(object_loader load_object, kernel_runner run_kernel)
if(msgtype == MSGTYPE_REQUEST_IDENT) {
send_char(MSGTYPE_IDENT);
send_int(0x41524f52); /* "AROR" - ARTIQ runtime on OpenRISC */
#ifdef ARTIQ_AMP
#warning TODO
send_int(125*1000*1000);
send_char(0);
send_char(1);
#else
send_int(rtio_frequency_i_read());
send_char(rtio_frequency_fn_read());
send_char(rtio_frequency_fd_read());
#endif
} else if(msgtype == MSGTYPE_LOAD_OBJECT)
receive_and_load_object(load_object);
else if(msgtype == MSGTYPE_RUN_KERNEL)
4 changes: 2 additions & 2 deletions soc/targets/artiq_kc705.py
Original file line number Diff line number Diff line change
@@ -98,7 +98,7 @@ class UP(_Peripherals):
def __init__(self, *args, **kwargs):
_Peripherals.__init__(self, *args, **kwargs)

rtio_csrs = self.rtio.get_csrs() + self.rtio.get_kernel_csrs()
rtio_csrs = self.rtio.get_csrs()
self.submodules.rtiowb = wbgen.Bank(rtio_csrs)
self.add_wb_slave(mem_decoder(self.mem_map["rtio"]), self.rtiowb.bus)
self.add_csr_region("rtio", self.mem_map["rtio"] + 0x80000000, 32, rtio_csrs)
@@ -127,7 +127,7 @@ def __init__(self, platform, *args, **kwargs):
self.kernel_cpu.add_wb_slave(mem_decoder(self.mem_map["mailbox"]), self.mailbox.i2)
self.add_memory_region("mailbox", self.mem_map["mailbox"] + 0x80000000, 4)

rtio_csrs = self.rtio.get_kernel_csrs()
rtio_csrs = self.rtio.get_csrs()
self.submodules.rtiowb = wbgen.Bank(rtio_csrs)
self.kernel_cpu.add_wb_slave(mem_decoder(self.mem_map["rtio"]), self.rtiowb.bus)
self.add_csr_region("rtio", self.mem_map["rtio"] + 0x80000000, 32, rtio_csrs)
4 changes: 2 additions & 2 deletions soc/targets/artiq_pipistrello.py
Original file line number Diff line number Diff line change
@@ -125,7 +125,7 @@ class UP(_Peripherals):
def __init__(self, platform, **kwargs):
_Peripherals.__init__(self, platform, **kwargs)

rtio_csrs = self.rtio.get_csrs() + self.rtio.get_kernel_csrs()
rtio_csrs = self.rtio.get_csrs()
self.submodules.rtiowb = wbgen.Bank(rtio_csrs)
self.add_wb_slave(mem_decoder(self.mem_map["rtio"]), self.rtiowb.bus)
self.add_csr_region("rtio", self.mem_map["rtio"] + 0x80000000, 32,
@@ -158,7 +158,7 @@ def __init__(self, platform, *args, **kwargs):
self.add_memory_region("mailbox",
self.mem_map["mailbox"] + 0x80000000, 4)

rtio_csrs = self.rtio.get_kernel_csrs()
rtio_csrs = self.rtio.get_csrs()
self.submodules.rtiowb = wbgen.Bank(rtio_csrs)
self.kernel_cpu.add_wb_slave(mem_decoder(self.mem_map["rtio"]),
self.rtiowb.bus)
2 changes: 1 addition & 1 deletion soc/targets/artiq_ppro.py
Original file line number Diff line number Diff line change
@@ -112,7 +112,7 @@ def __init__(self, platform, cpu_type="or1k",
clk_freq=125000000,
counter_width=32)

rtio_csrs = self.rtio.get_csrs() + self.rtio.get_kernel_csrs()
rtio_csrs = self.rtio.get_csrs()
self.submodules.rtiowb = wbgen.Bank(rtio_csrs)
self.add_wb_slave(mem_decoder(self.mem_map["rtio"]), self.rtiowb.bus)
self.add_csr_region("rtio", self.mem_map["rtio"] + 0x80000000,

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