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sbourdeauducqsbourdeauducq
committedApr 16, 2015
coredevice,runtime: put ref_period into the ddb
·
8.00.1
1 parent 485381f commit 546996f

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10 files changed

+14
-60
lines changed

10 files changed

+14
-60
lines changed
 

Diff for: ‎artiq/coredevice/comm_generic.py

+1-8
Original file line numberDiff line numberDiff line change
@@ -108,12 +108,7 @@ def get_runtime_env(self):
108108
if runtime_id != "AROR":
109109
raise UnsupportedDevice("Unsupported runtime ID: {}"
110110
.format(runtime_id))
111-
ref_freq_i, ref_freq_fn, ref_freq_fd = struct.unpack(
112-
">lBB", self._read(6))
113-
ref_freq = (ref_freq_i + Fraction(ref_freq_fn, ref_freq_fd))*units.Hz
114-
ref_period = 1/ref_freq
115-
logger.debug("environment ref_period: %s", ref_period)
116-
return Environment(ref_period)
111+
return Environment()
117112

118113
def switch_clock(self, external):
119114
self._write(struct.pack(
@@ -140,8 +135,6 @@ def run(self, kname):
140135
self._write(struct.pack(">B", ord(c)))
141136
logger.debug("running kernel: %s", kname)
142137

143-
144-
145138
def _receive_rpc_values(self):
146139
r = []
147140
while True:

Diff for: ‎artiq/coredevice/core.py

+4-8
Original file line numberDiff line numberDiff line change
@@ -47,19 +47,15 @@ def _no_debug_unparse(label, node):
4747
class Core(AutoDB):
4848
class DBKeys:
4949
comm = Device()
50-
external_clock = Parameter(None)
50+
ref_period = Argument()
51+
external_clock = Argument(False)
5152

5253
def build(self):
5354
self.runtime_env = self.comm.get_runtime_env()
5455
self.core = self
5556
self.comm.core = self
56-
57-
if self.external_clock is None:
58-
self.ref_period = self.runtime_env.internal_ref_period
59-
self.comm.switch_clock(False)
60-
else:
61-
self.ref_period = 1/self.external_clock
62-
self.comm.switch_clock(True)
57+
58+
self.comm.switch_clock(self.external_clock)
6359
self.initial_time = int64(self.runtime_env.warmup_time/self.ref_period)
6460

6561
def transform_stack(self, func_def, rpc_map, exception_map,

Diff for: ‎artiq/coredevice/runtime.py

+2-4
Original file line numberDiff line numberDiff line change
@@ -190,9 +190,8 @@ def _debug_dump_obj(obj):
190190

191191

192192
class Environment(LinkInterface):
193-
def __init__(self, internal_ref_period):
193+
def __init__(self):
194194
self.cpu_type = "or1k"
195-
self.internal_ref_period = internal_ref_period
196195
# allow 1ms for all initial DDS programming
197196
self.warmup_time = 1*units.ms
198197

@@ -203,5 +202,4 @@ def emit_object(self):
203202
return obj
204203

205204
def __repr__(self):
206-
return "<Environment {} {}>".format(self.cpu_type,
207-
str(1/self.ref_period))
205+
return "<Environment {}>".format(self.cpu_type)

Diff for: ‎artiq/gateware/rtio/core.py

-23
Original file line numberDiff line numberDiff line change
@@ -1,5 +1,3 @@
1-
from fractions import Fraction
2-
31
from migen.fhdl.std import *
42
from migen.bank.description import *
53
from migen.genlib.misc import optree
@@ -255,13 +253,6 @@ def __init__(self, interface, ofifo_depth=64, ififo_depth=64):
255253
self.ififo_depth = ififo_depth
256254

257255

258-
class _CSRs(AutoCSR):
259-
def __init__(self):
260-
self.frequency_i = CSRStatus(32)
261-
self.frequency_fn = CSRStatus(8)
262-
self.frequency_fd = CSRStatus(8)
263-
264-
265256
class _KernelCSRs(AutoCSR):
266257
def __init__(self, chan_sel_width,
267258
data_width, address_width, full_ts_width):
@@ -300,7 +291,6 @@ def __init__(self, channels, clk_freq, counter_width=63,
300291
for c in channels)
301292

302293
# CSRs
303-
self.csrs = _CSRs()
304294
self.kcsrs = _KernelCSRs(bits_for(len(channels)-1),
305295
data_width, address_width,
306296
counter_width + fine_ts_width)
@@ -405,18 +395,5 @@ def __init__(self, channels, clk_freq, counter_width=63,
405395
<< fine_ts_width)
406396
)
407397

408-
# Frequency CSRs
409-
clk_freq = Fraction(clk_freq).limit_denominator(255)
410-
clk_freq_i = int(clk_freq)
411-
clk_freq_f = clk_freq - clk_freq_i
412-
self.comb += [
413-
self.csrs.frequency_i.status.eq(clk_freq_i),
414-
self.csrs.frequency_fn.status.eq(clk_freq_f.numerator),
415-
self.csrs.frequency_fd.status.eq(clk_freq_f.denominator)
416-
]
417-
418398
def get_csrs(self):
419-
return self.csrs.get_csrs()
420-
421-
def get_kernel_csrs(self):
422399
return self.kcsrs.get_csrs()

Diff for: ‎benchmarks/ddb.pyon

+1-1
Original file line numberDiff line numberDiff line change
@@ -9,7 +9,7 @@
99
"type": "local",
1010
"module": "artiq.coredevice.core",
1111
"class": "Core",
12-
"arguments": {}
12+
"arguments": {"ref_period": Quantity(Fraction(8, 1000000000), "s")}
1313
},
1414

1515
"pmt0": {

Diff for: ‎examples/master/ddb.pyon

+1-1
Original file line numberDiff line numberDiff line change
@@ -9,7 +9,7 @@
99
"type": "local",
1010
"module": "artiq.coredevice.core",
1111
"class": "Core",
12-
"arguments": {}
12+
"arguments": {"ref_period": Quantity(Fraction(8, 1000000000), "s")}
1313
},
1414

1515
"pmt0": {

Diff for: ‎soc/runtime/comm_serial.c

-10
Original file line numberDiff line numberDiff line change
@@ -178,16 +178,6 @@ void comm_serve(object_loader load_object, kernel_runner run_kernel)
178178
if(msgtype == MSGTYPE_REQUEST_IDENT) {
179179
send_char(MSGTYPE_IDENT);
180180
send_int(0x41524f52); /* "AROR" - ARTIQ runtime on OpenRISC */
181-
#ifdef ARTIQ_AMP
182-
#warning TODO
183-
send_int(125*1000*1000);
184-
send_char(0);
185-
send_char(1);
186-
#else
187-
send_int(rtio_frequency_i_read());
188-
send_char(rtio_frequency_fn_read());
189-
send_char(rtio_frequency_fd_read());
190-
#endif
191181
} else if(msgtype == MSGTYPE_LOAD_OBJECT)
192182
receive_and_load_object(load_object);
193183
else if(msgtype == MSGTYPE_RUN_KERNEL)

Diff for: ‎soc/targets/artiq_kc705.py

+2-2
Original file line numberDiff line numberDiff line change
@@ -98,7 +98,7 @@ class UP(_Peripherals):
9898
def __init__(self, *args, **kwargs):
9999
_Peripherals.__init__(self, *args, **kwargs)
100100

101-
rtio_csrs = self.rtio.get_csrs() + self.rtio.get_kernel_csrs()
101+
rtio_csrs = self.rtio.get_csrs()
102102
self.submodules.rtiowb = wbgen.Bank(rtio_csrs)
103103
self.add_wb_slave(mem_decoder(self.mem_map["rtio"]), self.rtiowb.bus)
104104
self.add_csr_region("rtio", self.mem_map["rtio"] + 0x80000000, 32, rtio_csrs)
@@ -127,7 +127,7 @@ def __init__(self, platform, *args, **kwargs):
127127
self.kernel_cpu.add_wb_slave(mem_decoder(self.mem_map["mailbox"]), self.mailbox.i2)
128128
self.add_memory_region("mailbox", self.mem_map["mailbox"] + 0x80000000, 4)
129129

130-
rtio_csrs = self.rtio.get_kernel_csrs()
130+
rtio_csrs = self.rtio.get_csrs()
131131
self.submodules.rtiowb = wbgen.Bank(rtio_csrs)
132132
self.kernel_cpu.add_wb_slave(mem_decoder(self.mem_map["rtio"]), self.rtiowb.bus)
133133
self.add_csr_region("rtio", self.mem_map["rtio"] + 0x80000000, 32, rtio_csrs)

Diff for: ‎soc/targets/artiq_pipistrello.py

+2-2
Original file line numberDiff line numberDiff line change
@@ -125,7 +125,7 @@ class UP(_Peripherals):
125125
def __init__(self, platform, **kwargs):
126126
_Peripherals.__init__(self, platform, **kwargs)
127127

128-
rtio_csrs = self.rtio.get_csrs() + self.rtio.get_kernel_csrs()
128+
rtio_csrs = self.rtio.get_csrs()
129129
self.submodules.rtiowb = wbgen.Bank(rtio_csrs)
130130
self.add_wb_slave(mem_decoder(self.mem_map["rtio"]), self.rtiowb.bus)
131131
self.add_csr_region("rtio", self.mem_map["rtio"] + 0x80000000, 32,
@@ -158,7 +158,7 @@ def __init__(self, platform, *args, **kwargs):
158158
self.add_memory_region("mailbox",
159159
self.mem_map["mailbox"] + 0x80000000, 4)
160160

161-
rtio_csrs = self.rtio.get_kernel_csrs()
161+
rtio_csrs = self.rtio.get_csrs()
162162
self.submodules.rtiowb = wbgen.Bank(rtio_csrs)
163163
self.kernel_cpu.add_wb_slave(mem_decoder(self.mem_map["rtio"]),
164164
self.rtiowb.bus)

Diff for: ‎soc/targets/artiq_ppro.py

+1-1
Original file line numberDiff line numberDiff line change
@@ -112,7 +112,7 @@ def __init__(self, platform, cpu_type="or1k",
112112
clk_freq=125000000,
113113
counter_width=32)
114114

115-
rtio_csrs = self.rtio.get_csrs() + self.rtio.get_kernel_csrs()
115+
rtio_csrs = self.rtio.get_csrs()
116116
self.submodules.rtiowb = wbgen.Bank(rtio_csrs)
117117
self.add_wb_slave(mem_decoder(self.mem_map["rtio"]), self.rtiowb.bus)
118118
self.add_csr_region("rtio", self.mem_map["rtio"] + 0x80000000,

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