m-labs · Apr 14, 2015 · Apr 14, 2015
diff --git a/artiq/coredevice/rtio.py b/artiq/coredevice/rtio.py
@@ -21,17 +21,17 @@ def build(self):
 
     @kernel
     def _set_oe(self):
-        syscall("rtio_oe", self.channel, True)
+        syscall("rtio_set_oe", time_to_cycles(now()), self.channel, True)
 
     @kernel
-    def set_value(self, t, value):
-        """Sets the value of the RTIO channel.
+    def set_o(self, t, value):
+        """Sets the output value of the RTIO channel.
 
         :param t: timestamp in RTIO cycles (64-bit integer).
         :param value: value to set at the output.
 
         """
-        syscall("rtio_set", t, self.channel, value)
+        syscall("rtio_set_o", t, self.channel, value)
 
     @kernel
     def on(self, t):
@@ -40,7 +40,7 @@ def on(self, t):
         :param t: timestamp in RTIO cycles (64-bit integer).
 
         """
-        self.set_value(t, 1)
+        self.set_o(t, 1)
 
     @kernel
     def off(self, t):
@@ -49,28 +49,10 @@ def off(self, t):
         :param t: timestamp in RTIO cycles (64-bit integer).
 
         """
-        self.set_value(t, 0)
+        self.set_o(t, 0)
 
 
-class _RTIOBase(AutoDB):
-    class DBKeys:
-        core = Device()
-        channel = Argument()
-
-    def build(self):
-        self.previous_timestamp = int64(0)  # in RTIO cycles
-
-    @kernel
-    def _set_oe(self, oe):
-        syscall("rtio_oe", self.channel, oe)
-
-    @kernel
-    def _set_value(self, value):
-        syscall("rtio_set", time_to_cycles(now()), self.channel, value)
-        self.previous_timestamp = time_to_cycles(now())
-
-
-class RTIOOut(_RTIOBase):
+class RTIOOut(AutoDB):
     """RTIO output driver.
 
     Configures the corresponding RTIO channel as output on the core device and
@@ -85,9 +67,22 @@ class RTIOOut(_RTIOBase):
     :param channel: channel number
 
     """
+    class DBKeys:
+        core = Device()
+        channel = Argument()
+
     def build(self):
-        _RTIOBase.build(self)
-        self._set_oe(True)
+        self.previous_timestamp = int64(0)  # in RTIO cycles
+        self._set_oe()
+
+    @kernel
+    def _set_oe(self):
+        syscall("rtio_set_oe", time_to_cycles(now()), self.channel, True)
+
+    @kernel
+    def _set_o(self, value):
+        syscall("rtio_set_o", time_to_cycles(now()), self.channel, value)
+        self.previous_timestamp = time_to_cycles(now())
 
     @kernel
     def sync(self):
@@ -96,24 +91,19 @@ def sync(self):
         This function is useful to synchronize CPU-controlled devices (such as
         the AD9858 DDS bus) with related RTIO controls (such as RF switches at
         the output of the DDS).
-
         """
         while syscall("rtio_get_counter") < self.previous_timestamp:
             pass
 
     @kernel
     def on(self):
-        """Sets the output to a logic high state.
-
-        """
-        self._set_value(1)
+        """Sets the output to a logic high state."""
+        self._set_o(1)
 
     @kernel
     def off(self):
-        """Sets the output to a logic low state.
-
-        """
-        self._set_value(0)
+        """Sets the output to a logic low state."""
+        self._set_o(0)
 
     @kernel
     def pulse(self, duration):
@@ -125,7 +115,7 @@ def pulse(self, duration):
         self.off()
 
 
-class RTIOIn(_RTIOBase):
+class RTIOIn(AutoDB):
     """RTIO input driver.
 
     Configures the corresponding RTIO channel as input on the core device and
@@ -134,48 +124,51 @@ class RTIOIn(_RTIOBase):
 
     :param core: core device
     :param channel: channel number
-
     """
+    class DBKeys:
+        core = Device()
+        channel = Argument()
+
     def build(self):
-        _RTIOBase.build(self)
-        self._set_oe(False)
+        self.previous_timestamp = int64(0)  # in RTIO cycles
+        self._set_oe()
+
+    @kernel
+    def _set_oe(self):
+        syscall("rtio_set_oe", time_to_cycles(now()), self.channel, False)
+
+    @kernel
+    def _set_sensitivity(self, value):
+        syscall("rtio_set_sensitivity", time_to_cycles(now()), self.channel, value)
+        self.previous_timestamp = time_to_cycles(now())
 
     @kernel
     def gate_rising(self, duration):
         """Register rising edge events for the specified duration.
 
         """
-        self._set_value(1)
+        self._set_sensitivity(1)
         delay(duration)
-        self._set_value(0)
+        self._set_sensitivity(0)
 
     @kernel
     def gate_falling(self, duration):
         """Register falling edge events for the specified duration.
 
         """
-        self._set_value(2)
+        self._set_sensitivity(2)
         delay(duration)
-        self._set_value(0)
+        self._set_sensitivity(0)
 
     @kernel
     def gate_both(self, duration):
         """Register both rising and falling edge events for the specified
         duration.
 
         """
-        self._set_value(3)
+        self._set_sensitivity(3)
         delay(duration)
-        self._set_value(0)
-
-    @kernel
-    def pileup_count(self):
-        """Returns the number of pileup events (a system clock cycle with too
-        many input transitions) since the last call to this function for this
-        channel (or since the last RTIO reset).
-
-        """
-        return syscall("rtio_pileup_count", self.channel)
+        self._set_sensitivity(0)
 
     @kernel
     def count(self):

diff --git a/artiq/coredevice/runtime.py b/artiq/coredevice/runtime.py
@@ -12,11 +12,11 @@
 llvm.initialize_all_asmprinters()
 
 _syscalls = {
-    "rtio_oe": "ib:n",
-    "rtio_set": "Iii:n",
+    "rtio_set_o": "Iii:n",
+    "rtio_set_oe": "Iib:n",
+    "rtio_set_sensitivity": "Iii:n",
     "rtio_get_counter": "n:I",
     "rtio_get": "iI:I",
-    "rtio_pileup_count": "i:i",
     "dds_phase_clear_en": "ib:n",
     "dds_program": "Iiiiibb:n",
 }

diff --git a/artiq/gateware/rtio/__init__.py b/artiq/gateware/rtio/__init__.py
@@ -1,2 +1 @@
-from artiq.gateware.rtio import phy
-from artiq.gateware.rtio.core import RTIO
+from artiq.gateware.rtio.core import Channel, RTIO