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revert fhdl/verilog: avoid reg initialization in printheader when res…
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…et is not an int. (sorry merge issue)
enjoy-digital committed Apr 13, 2015
1 parent 4824867 commit 3f15699
Showing 1 changed file with 1 addition and 5 deletions.
6 changes: 1 addition & 5 deletions migen/fhdl/verilog.py
Original file line number Diff line number Diff line change
@@ -178,11 +178,7 @@ def _printheader(f, ios, name, ns):
if sig in wires:
r += "wire " + _printsig(ns, sig) + ";\n"
else:
if isinstance(sig.reset, int):
resetexpr = " = " + _printexpr(ns, sig.reset)[0]
else:
resetexpr = ""
r += "reg " + _printsig(ns, sig) + resetexpr + ";\n"
r += "reg " + _printsig(ns, sig) + " = " + _printexpr(ns, sig.reset)[0] + ";\n"
r += "\n"
return r

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