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  • 12 commits
  • 122 files changed
  • 1 contributor

Commits on Apr 10, 2015

  1. fhdl/verilog: avoid reg initialization in printheader when reset is n…

    …ot an int.
    
    We should be able to reset a signal with the value of another one. Without this change it's not possible to do so since synthesis tools do not support initializing a signal from another one.
    enjoy-digital committed Apr 10, 2015
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Commits on Apr 13, 2015

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  3. global: pep8 (E302)

    enjoy-digital committed Apr 13, 2015
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    1051878 View commit details
  4. global: pep8 (E231)

    enjoy-digital committed Apr 13, 2015
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  5. global: pep8 (E401)

    enjoy-digital committed Apr 13, 2015
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  6. global: pep8 (E222)

    enjoy-digital committed Apr 13, 2015
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  7. global: pep8 (E225)

    enjoy-digital committed Apr 13, 2015
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  9. global: pep8 (E265)

    enjoy-digital committed Apr 13, 2015
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  10. global: more pep8

    we will have to continue the work... volunteers are welcome :)
    enjoy-digital committed Apr 13, 2015
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Showing with 10,524 additions and 10,053 deletions.
  1. +6 −6 doc/conf.py
  2. +17 −16 examples/basic/arrays.py
  3. +13 −12 examples/basic/complex.py
  4. +19 −18 examples/basic/fsm.py
  5. +10 −9 examples/basic/graycounter.py
  6. +8 −6 examples/basic/local_cd.py
  7. +8 −7 examples/basic/memory.py
  8. +27 −22 examples/basic/namer.py
  9. +9 −7 examples/basic/psync.py
  10. +12 −11 examples/basic/record.py
  11. +11 −10 examples/basic/reslice.py
  12. +15 −14 examples/basic/simple_gpio.py
  13. +5 −4 examples/basic/tristate.py
  14. +8 −7 examples/basic/two_dividers.py
  15. +67 −54 examples/dataflow/dma.py
  16. +26 −22 examples/dataflow/misc.py
  17. +45 −40 examples/dataflow/structuring.py
  18. +39 −36 examples/sim/abstract_transactions_wb.py
  19. +19 −18 examples/sim/basic1.py
  20. +18 −17 examples/sim/basic2.py
  21. +28 −23 examples/sim/dataflow.py
  22. +48 −46 examples/sim/fir.py
  23. +19 −18 examples/sim/memory.py
  24. +18 −17 mibuild/altera/platform.py
  25. +5 −4 mibuild/altera/programmer.py
  26. +76 −69 mibuild/altera/quartus.py
  27. +266 −252 mibuild/generic_platform.py
  28. +26 −25 mibuild/generic_programmer.py
  29. +26 −22 mibuild/lattice/common.py
  30. +76 −68 mibuild/lattice/diamond.py
  31. +18 −17 mibuild/lattice/platform.py
  32. +40 −38 mibuild/lattice/programmer.py
  33. +137 −136 mibuild/platforms/apf27.py
  34. +165 −164 mibuild/platforms/apf51.py
  35. +89 −88 mibuild/platforms/de0nano.py
  36. +388 −387 mibuild/platforms/kc705.py
  37. +114 −114 mibuild/platforms/lx9_microboard.py
  38. +136 −135 mibuild/platforms/m1.py
  39. +111 −110 mibuild/platforms/minispartan6.py
  40. +172 −171 mibuild/platforms/mixxeo.py
  41. +51 −50 mibuild/platforms/ml605.py
  42. +48 −47 mibuild/platforms/papilio_pro.py
  43. +124 −123 mibuild/platforms/pipistrello.py
  44. +122 −121 mibuild/platforms/rhino.py
  45. +27 −26 mibuild/platforms/roach.py
  46. +34 −32 mibuild/platforms/sim.py
  47. +130 −130 mibuild/platforms/usrp_b100.py
  48. +77 −76 mibuild/platforms/versa.py
  49. +134 −134 mibuild/platforms/zedboard.py
  50. +82 −81 mibuild/platforms/ztex_115d.py
  51. +13 −12 mibuild/sim/platform.py
  52. +114 −109 mibuild/sim/verilator.py
  53. +31 −25 mibuild/tools.py
  54. +78 −65 mibuild/xilinx/common.py
  55. +152 −143 mibuild/xilinx/ise.py
  56. +22 −21 mibuild/xilinx/platform.py
  57. +69 −60 mibuild/xilinx/programmer.py
  58. +117 −110 mibuild/xilinx/vivado.py
  59. +49 −47 migen/actorlib/dma_wishbone.py
  60. +48 −45 migen/actorlib/fifo.py
  61. +52 −51 migen/actorlib/misc.py
  62. +99 −93 migen/actorlib/sim.py
  63. +158 −152 migen/actorlib/spi.py
  64. +246 −237 migen/actorlib/structuring.py
  65. +19 −17 migen/bank/bank.py
  66. +59 −57 migen/bank/csrgen.py
  67. +126 −118 migen/bank/description.py
  68. +64 −58 migen/bank/eventmanager.py
  69. +18 −17 migen/bank/wbgen.py
  70. +118 −114 migen/bus/csr.py
  71. +29 −27 migen/bus/memory.py
  72. +16 −13 migen/bus/transactions.py
  73. +298 −286 migen/bus/wishbone.py
  74. +20 −19 migen/bus/wishbone2csr.py
  75. +194 −187 migen/fhdl/bitcontainer.py
  76. +96 −90 migen/fhdl/decorators.py
  77. +179 −169 migen/fhdl/edif.py
  78. +157 −145 migen/fhdl/module.py
  79. +214 −200 migen/fhdl/namer.py
  80. +32 −31 migen/fhdl/simplify.py
  81. +315 −308 migen/fhdl/specials.py
  82. +1 −1 migen/fhdl/std.py
  83. +553 −533 migen/fhdl/structure.py
  84. +210 −187 migen/fhdl/tools.py
  85. +99 −94 migen/fhdl/tracer.py
  86. +286 −268 migen/fhdl/verilog.py
  87. +188 −186 migen/fhdl/visit.py
  88. +156 −146 migen/flow/actor.py
  89. +32 −30 migen/flow/hooks.py
  90. +56 −54 migen/flow/isd.py
  91. +311 −307 migen/flow/network.py
  92. +41 −39 migen/flow/perftools.py
  93. +86 −81 migen/flow/plumbing.py
  94. +4 −4 migen/flow/transactions.py
  95. +84 −79 migen/genlib/cdc.py
  96. +84 −80 migen/genlib/coding.py
  97. +49 −47 migen/genlib/complex.py
  98. +33 −32 migen/genlib/divider.py
  99. +210 −205 migen/genlib/fifo.py
  100. +126 −121 migen/genlib/fsm.py
  101. +78 −73 migen/genlib/io.py
  102. +139 −139 migen/genlib/mhamgen.py
  103. +97 −89 migen/genlib/misc.py
  104. +151 −146 migen/genlib/record.py
  105. +12 −11 migen/genlib/resetsync.py
  106. +65 −63 migen/genlib/rob.py
  107. +32 −31 migen/genlib/roundrobin.py
  108. +58 −57 migen/genlib/sort.py
  109. +182 −179 migen/sim/generic.py
  110. +32 −32 migen/sim/icarus.py
  111. +137 −121 migen/sim/ipc.py
  112. +101 −98 migen/sim/upper.py
  113. +14 −12 migen/test/support.py
  114. +50 −44 migen/test/test_actor.py
  115. +92 −88 migen/test/test_coding.py
  116. +46 −45 migen/test/test_fifo.py
  117. +39 −38 migen/test/test_signed.py
  118. +46 −44 migen/test/test_size.py
  119. +16 −15 migen/test/test_sort.py
  120. +31 −27 migen/util/misc.py
  121. +100 −96 migen/util/treeviz.py
  122. +26 −25 setup.py
12 changes: 6 additions & 6 deletions doc/conf.py
Original file line number Diff line number Diff line change
@@ -26,12 +26,12 @@
# Add any Sphinx extension module names here, as strings. They can be extensions
# coming with Sphinx (named 'sphinx.ext.*') or your custom ones.
extensions = [
'sphinx.ext.pngmath',
'sphinx.ext.autodoc',
'sphinx.ext.doctest',
'sphinx.ext.autosummary',
'numpydoc', # to preprocess docstrings
]
'sphinx.ext.pngmath',
'sphinx.ext.autodoc',
'sphinx.ext.doctest',
'sphinx.ext.autosummary',
'numpydoc', # to preprocess docstrings
]

# Add any paths that contain templates here, relative to this directory.
templates_path = ['_templates']
33 changes: 17 additions & 16 deletions examples/basic/arrays.py
Original file line number Diff line number Diff line change
@@ -1,26 +1,27 @@
from migen.fhdl.std import *
from migen.fhdl import verilog


class Example(Module):
def __init__(self):
dx = 2
dy = 2
def __init__(self):
dx = 2
dy = 2

x = Signal(max=dx)
y = Signal(max=dy)
out = Signal()
x = Signal(max=dx)
y = Signal(max=dy)
out = Signal()

my_2d_array = Array(Array(Signal() for a in range(dx)) for b in range(dy))
self.comb += out.eq(my_2d_array[x][y])
my_2d_array = Array(Array(Signal() for a in range(dx)) for b in range(dy))
self.comb += out.eq(my_2d_array[x][y])

we = Signal()
inp = Signal()
self.sync += If(we,
my_2d_array[x][y].eq(inp)
)
we = Signal()
inp = Signal()
self.sync += If(we,
my_2d_array[x][y].eq(inp)
)

ina = Array(Signal() for a in range(dx))
outa = Array(Signal() for a in range(dy))
self.specials += Instance("test", o_O=outa[y], i_I=ina[x])
ina = Array(Signal() for a in range(dx))
outa = Array(Signal() for a in range(dy))
self.specials += Instance("test", o_O=outa[y], i_I=ina[x])

print(verilog.convert(Example()))
25 changes: 13 additions & 12 deletions examples/basic/complex.py
Original file line number Diff line number Diff line change
@@ -2,18 +2,19 @@
from migen.genlib.complex import *
from migen.fhdl import verilog


class Example(Module):
def __init__(self):
w = Complex(32, 42)
A = SignalC(16)
B = SignalC(16)
Bw = SignalC(16)
C = SignalC(16)
D = SignalC(16)
self.comb += Bw.eq(B*w)
self.sync += [
C.eq(A + Bw),
D.eq(A - Bw)
]
def __init__(self):
w = Complex(32, 42)
A = SignalC(16)
B = SignalC(16)
Bw = SignalC(16)
C = SignalC(16)
D = SignalC(16)
self.comb += Bw.eq(B*w)
self.sync += [
C.eq(A + Bw),
D.eq(A - Bw)
]

print(verilog.convert(Example()))
37 changes: 19 additions & 18 deletions examples/basic/fsm.py
Original file line number Diff line number Diff line change
@@ -2,28 +2,29 @@
from migen.fhdl import verilog
from migen.genlib.fsm import FSM, NextState, NextValue


class Example(Module):
def __init__(self):
self.s = Signal()
self.counter = Signal(8)
def __init__(self):
self.s = Signal()
self.counter = Signal(8)

myfsm = FSM()
self.submodules += myfsm
myfsm = FSM()
self.submodules += myfsm

myfsm.act("FOO",
self.s.eq(1),
NextState("BAR")
)
myfsm.act("BAR",
self.s.eq(0),
NextValue(self.counter, self.counter + 1),
NextState("FOO")
)
myfsm.act("FOO",
self.s.eq(1),
NextState("BAR")
)
myfsm.act("BAR",
self.s.eq(0),
NextValue(self.counter, self.counter + 1),
NextState("FOO")
)

self.be = myfsm.before_entering("FOO")
self.ae = myfsm.after_entering("FOO")
self.bl = myfsm.before_leaving("FOO")
self.al = myfsm.after_leaving("FOO")
self.be = myfsm.before_entering("FOO")
self.ae = myfsm.after_entering("FOO")
self.bl = myfsm.before_leaving("FOO")
self.al = myfsm.after_leaving("FOO")

example = Example()
print(verilog.convert(example, {example.s, example.counter, example.be, example.ae, example.bl, example.al}))
19 changes: 10 additions & 9 deletions examples/basic/graycounter.py
Original file line number Diff line number Diff line change
@@ -4,16 +4,17 @@
from migen.genlib.cdc import GrayCounter
from migen.sim.generic import run_simulation


class TB(Module):
def __init__(self, width=3):
self.width = width
self.submodules.gc = GrayCounter(self.width)
self.prng = Random(7345)
def __init__(self, width=3):
self.width = width
self.submodules.gc = GrayCounter(self.width)
self.prng = Random(7345)

def do_simulation(self, selfp):
print("{0:0{1}b} CE={2} bin={3}".format(selfp.gc.q,
self.width, selfp.gc.ce, selfp.gc.q_binary))
selfp.gc.ce = self.prng.getrandbits(1)
def do_simulation(self, selfp):
print("{0:0{1}b} CE={2} bin={3}".format(selfp.gc.q,
self.width, selfp.gc.ce, selfp.gc.q_binary))
selfp.gc.ce = self.prng.getrandbits(1)

if __name__ == "__main__":
run_simulation(TB(), ncycles=35)
run_simulation(TB(), ncycles=35)
14 changes: 8 additions & 6 deletions examples/basic/local_cd.py
Original file line number Diff line number Diff line change
@@ -2,15 +2,17 @@
from migen.fhdl import verilog
from migen.genlib.divider import Divider


class CDM(Module):
def __init__(self):
self.submodules.divider = Divider(5)
self.clock_domains.cd_sys = ClockDomain(reset_less=True)
def __init__(self):
self.submodules.divider = Divider(5)
self.clock_domains.cd_sys = ClockDomain(reset_less=True)


class MultiMod(Module):
def __init__(self):
self.submodules.foo = CDM()
self.submodules.bar = CDM()
def __init__(self):
self.submodules.foo = CDM()
self.submodules.bar = CDM()

mm = MultiMod()
print(verilog.convert(mm, {mm.foo.cd_sys.clk, mm.bar.cd_sys.clk}))
15 changes: 8 additions & 7 deletions examples/basic/memory.py
Original file line number Diff line number Diff line change
@@ -1,14 +1,15 @@
from migen.fhdl.std import *
from migen.fhdl import verilog


class Example(Module):
def __init__(self):
self.specials.mem = Memory(32, 100, init=[5, 18, 32])
p1 = self.mem.get_port(write_capable=True, we_granularity=8)
p2 = self.mem.get_port(has_re=True, clock_domain="rd")
self.specials += p1, p2
self.ios = {p1.adr, p1.dat_r, p1.we, p1.dat_w,
p2.adr, p2.dat_r, p2.re}
def __init__(self):
self.specials.mem = Memory(32, 100, init=[5, 18, 32])
p1 = self.mem.get_port(write_capable=True, we_granularity=8)
p2 = self.mem.get_port(has_re=True, clock_domain="rd")
self.specials += p1, p2
self.ios = {p1.adr, p1.dat_r, p1.we, p1.dat_w,
p2.adr, p2.dat_r, p2.re}

example = Example()
print(verilog.convert(example, example.ios))
49 changes: 27 additions & 22 deletions examples/basic/namer.py
Original file line number Diff line number Diff line change
@@ -2,36 +2,41 @@
from migen.fhdl import verilog
from migen.genlib.misc import optree


def gen_list(n):
s = [Signal() for i in range(n)]
return s
s = [Signal() for i in range(n)]
return s


def gen_2list(n):
s = [Signal(2) for i in range(n)]
return s
s = [Signal(2) for i in range(n)]
return s


class Foo:
def __init__(self):
la = gen_list(3)
lb = gen_2list(2)
self.sigs = la + lb
def __init__(self):
la = gen_list(3)
lb = gen_2list(2)
self.sigs = la + lb


class Bar:
def __init__(self):
self.sigs = gen_list(2)
def __init__(self):
self.sigs = gen_list(2)


class Example(Module):
def __init__(self):
a = [Bar() for x in range(3)]
b = [Foo() for x in range(3)]
c = b
b = [Bar() for x in range(2)]

output = Signal()
allsigs = []
for lst in [a, b, c]:
for obj in lst:
allsigs.extend(obj.sigs)
self.comb += output.eq(optree("|", allsigs))
def __init__(self):
a = [Bar() for x in range(3)]
b = [Foo() for x in range(3)]
c = b
b = [Bar() for x in range(2)]

output = Signal()
allsigs = []
for lst in [a, b, c]:
for obj in lst:
allsigs.extend(obj.sigs)
self.comb += output.eq(optree("|", allsigs))

print(verilog.convert(Example()))
16 changes: 9 additions & 7 deletions examples/basic/psync.py
Original file line number Diff line number Diff line change
@@ -3,16 +3,18 @@
from migen.fhdl import verilog
from migen.genlib.cdc import *


class XilinxMultiRegImpl(MultiRegImpl):
def __init__(self, *args, **kwargs):
MultiRegImpl.__init__(self, *args, **kwargs)
self.specials += set(SynthesisDirective("attribute shreg_extract of {r} is no", r=r)
for r in self.regs)
def __init__(self, *args, **kwargs):
MultiRegImpl.__init__(self, *args, **kwargs)
self.specials += set(SynthesisDirective("attribute shreg_extract of {r} is no", r=r)
for r in self.regs)


class XilinxMultiReg:
@staticmethod
def lower(dr):
return XilinxMultiRegImpl(dr.i, dr.o, dr.odomain, dr.n)
@staticmethod
def lower(dr):
return XilinxMultiRegImpl(dr.i, dr.o, dr.odomain, dr.n)

ps = PulseSynchronizer("from", "to")
v = verilog.convert(ps, {ps.i, ps.o}, special_overrides={MultiReg: XilinxMultiReg})
23 changes: 12 additions & 11 deletions examples/basic/record.py
Original file line number Diff line number Diff line change
@@ -3,20 +3,21 @@
from migen.genlib.record import *

L = [
("position", [
("x", 10, DIR_M_TO_S),
("y", 10, DIR_M_TO_S),
]),
("color", 32, DIR_M_TO_S),
("stb", 1, DIR_M_TO_S),
("ack", 1, DIR_S_TO_M)
("position", [
("x", 10, DIR_M_TO_S),
("y", 10, DIR_M_TO_S),
]),
("color", 32, DIR_M_TO_S),
("stb", 1, DIR_M_TO_S),
("ack", 1, DIR_S_TO_M)
]


class Test(Module):
def __init__(self):
master = Record(L)
slave = Record(L)
self.comb += master.connect(slave)
def __init__(self):
master = Record(L)
slave = Record(L)
self.comb += master.connect(slave)

print(verilog.convert(Test()))
print(layout_len(L))
21 changes: 11 additions & 10 deletions examples/basic/reslice.py
Original file line number Diff line number Diff line change
@@ -1,16 +1,17 @@
from migen.fhdl.std import *
from migen.fhdl import verilog


class Example(Module):
def __init__(self):
a = Signal(3)
b = Signal(4)
c = Signal(5)
d = Signal(7)
s1 = c[:3][:2]
s2 = Cat(a, b)[:6]
s3 = Cat(s1, s2)[-5:]
self.comb += s3.eq(0)
self.comb += d.eq(Cat(d[::-1], Cat(s1[:1], s3[-4:])[:3]))
def __init__(self):
a = Signal(3)
b = Signal(4)
c = Signal(5)
d = Signal(7)
s1 = c[:3][:2]
s2 = Cat(a, b)[:6]
s3 = Cat(s1, s2)[-5:]
self.comb += s3.eq(0)
self.comb += d.eq(Cat(d[::-1], Cat(s1[:1], s3[-4:])[:3]))

print(verilog.convert(Example()))
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