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base repository: m-labs/migen
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head repository: m-labs/migen
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compare: 482486706ccf
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- 12 commits
- 122 files changed
- 1 contributor
Commits on Apr 10, 2015
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fhdl/verilog: avoid reg initialization in printheader when reset is n…
…ot an int. We should be able to reset a signal with the value of another one. Without this change it's not possible to do so since synthesis tools do not support initializing a signal from another one.
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Commits on Apr 13, 2015
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we will have to continue the work... volunteers are welcome :)
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