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enjoy-digitalenjoy-digital
committedApr 13, 2015
liteeth: more pep8 (when convenient), should be almost OK
·
0.120.1
1 parent 154d3d3 commit 2bd38f4

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19 files changed

+75
-31
lines changed

19 files changed

+75
-31
lines changed
 

‎misoclib/com/liteeth/common.py

+5-1
Original file line numberDiff line numberDiff line change
@@ -266,7 +266,11 @@ def eth_etherbone_packet_description(dw):
266266

267267
def eth_etherbone_packet_user_description(dw):
268268
param_layout = _layout_from_header(etherbone_packet_header)
269-
param_layout = _remove_from_layout(param_layout, "magic", "portsize", "addrsize", "version")
269+
param_layout = _remove_from_layout(param_layout,
270+
"magic",
271+
"portsize",
272+
"addrsize",
273+
"version")
270274
param_layout += eth_udp_user_description(dw).param_layout
271275
payload_layout = [
272276
("data", dw),

‎misoclib/com/liteeth/core/etherbone/packet.py

+3-1
Original file line numberDiff line numberDiff line change
@@ -120,7 +120,9 @@ def __init__(self):
120120
)
121121
fsm.act("DROP",
122122
depacketizer.source.ack.eq(1),
123-
If(depacketizer.source.stb & depacketizer.source.eop & depacketizer.source.ack,
123+
If(depacketizer.source.stb &
124+
depacketizer.source.eop &
125+
depacketizer.source.ack,
124126
NextState("IDLE")
125127
)
126128
)

‎misoclib/com/liteeth/core/etherbone/record.py

+4-2
Original file line numberDiff line numberDiff line change
@@ -29,7 +29,8 @@ def __init__(self, buffer_depth=256):
2929

3030
# # #
3131

32-
fifo = SyncFIFO(eth_etherbone_record_description(32), buffer_depth, buffered=True)
32+
fifo = SyncFIFO(eth_etherbone_record_description(32), buffer_depth,
33+
buffered=True)
3334
self.submodules += fifo
3435
self.comb += Record.connect(sink, fifo.sink)
3536

@@ -179,7 +180,8 @@ def __init__(self, endianness="big"):
179180
self.comb += [
180181
Record.connect(sender.source, packetizer.sink),
181182
Record.connect(packetizer.source, source),
182-
source.length.eq(sender.source.wcount*4 + 4 + etherbone_record_header_len), # XXX improve this
183+
# XXX improve this
184+
source.length.eq(sender.source.wcount*4 + 4 + etherbone_record_header_len),
183185
source.ip_address.eq(last_ip_address)
184186
]
185187
if endianness is "big":

‎misoclib/com/liteeth/core/icmp/__init__.py

+3-1
Original file line numberDiff line numberDiff line change
@@ -112,7 +112,9 @@ def __init__(self, ip_address):
112112
)
113113
fsm.act("DROP",
114114
depacketizer.source.ack.eq(1),
115-
If(depacketizer.source.stb & depacketizer.source.eop & depacketizer.source.ack,
115+
If(depacketizer.source.stb &
116+
depacketizer.source.eop &
117+
depacketizer.source.ack,
116118
NextState("IDLE")
117119
)
118120
)

‎misoclib/com/liteeth/core/ip/__init__.py

+6-2
Original file line numberDiff line numberDiff line change
@@ -91,7 +91,9 @@ def __init__(self, mac_address, ip_address, arp_table):
9191
)
9292
fsm.act("DROP",
9393
packetizer.source.ack.eq(1),
94-
If(packetizer.source.stb & packetizer.source.eop & packetizer.source.ack,
94+
If(packetizer.source.stb &
95+
packetizer.source.eop &
96+
packetizer.source.ack,
9597
NextState("IDLE")
9698
)
9799
)
@@ -167,7 +169,9 @@ def __init__(self, mac_address, ip_address):
167169
)
168170
fsm.act("DROP",
169171
depacketizer.source.ack.eq(1),
170-
If(depacketizer.source.stb & depacketizer.source.eop & depacketizer.source.ack,
172+
If(depacketizer.source.stb &
173+
depacketizer.source.eop &
174+
depacketizer.source.ack,
171175
NextState("IDLE")
172176
)
173177
)

‎misoclib/com/liteeth/core/udp/__init__.py

+3-1
Original file line numberDiff line numberDiff line change
@@ -112,7 +112,9 @@ def __init__(self, ip_address):
112112
)
113113
fsm.act("DROP",
114114
depacketizer.source.ack.eq(1),
115-
If(depacketizer.source.stb & depacketizer.source.eop & depacketizer.source.ack,
115+
If(depacketizer.source.stb &
116+
depacketizer.source.eop &
117+
depacketizer.source.ack,
116118
NextState("IDLE")
117119
)
118120
)

‎misoclib/com/liteeth/core/udp/crossbar.py

+4-2
Original file line numberDiff line numberDiff line change
@@ -33,13 +33,15 @@ def get_port(self, udp_port, dw=8):
3333
user_port = LiteEthUDPUserPort(dw)
3434
internal_port = LiteEthUDPUserPort(8)
3535
if dw != 8:
36-
converter = Converter(eth_udp_user_description(user_port.dw), eth_udp_user_description(8))
36+
converter = Converter(eth_udp_user_description(user_port.dw),
37+
eth_udp_user_description(8))
3738
self.submodules += converter
3839
self.comb += [
3940
Record.connect(user_port.sink, converter.sink),
4041
Record.connect(converter.source, internal_port.sink)
4142
]
42-
converter = Converter(eth_udp_user_description(8), eth_udp_user_description(user_port.dw))
43+
converter = Converter(eth_udp_user_description(8),
44+
eth_udp_user_description(user_port.dw))
4345
self.submodules += converter
4446
self.comb += [
4547
Record.connect(internal_port.source, converter.sink),

‎misoclib/com/liteeth/example_designs/test/make.py

+1-1
Original file line numberDiff line numberDiff line change
@@ -8,7 +8,7 @@ def _get_args():
88
parser.add_argument("-b", "--bridge", default="uart", help="Bridge to use")
99
parser.add_argument("--port", default="2", help="UART port")
1010
parser.add_argument("--baudrate", default=115200, help="UART baudrate")
11-
parser.add_argument("--ip_address", default="192.168.0.42", help="Etherbone IP address")
11+
parser.add_argument("--ip_address", default="192.168.0.42", help="Etherbone IP address")
1212
parser.add_argument("--udp_port", default=20000, help="Etherbone UDP port")
1313
parser.add_argument("--busword", default=32, help="CSR busword")
1414

‎misoclib/com/liteeth/generic/crossbar.py

+3-1
Original file line numberDiff line numberDiff line change
@@ -23,7 +23,9 @@ def do_finalize(self):
2323

2424
# RX dispatch
2525
sources = [port.source for port in self.users.values()]
26-
self.submodules.dispatcher = Dispatcher(self.master.sink, sources, one_hot=True)
26+
self.submodules.dispatcher = Dispatcher(self.master.sink,
27+
sources,
28+
one_hot=True)
2729
cases = {}
2830
cases["default"] = self.dispatcher.sel.eq(0)
2931
for i, (k, v) in enumerate(self.users.items()):

‎misoclib/com/liteeth/mac/core/__init__.py

+6-2
Original file line numberDiff line numberDiff line change
@@ -68,8 +68,12 @@ def __init__(self, phy, dw, endianness="big",
6868
# Converters
6969
if dw != phy.dw:
7070
reverse = endianness == "big"
71-
tx_converter = Converter(eth_phy_description(dw), eth_phy_description(phy.dw), reverse=reverse)
72-
rx_converter = Converter(eth_phy_description(phy.dw), eth_phy_description(dw), reverse=reverse)
71+
tx_converter = Converter(eth_phy_description(dw),
72+
eth_phy_description(phy.dw),
73+
reverse=reverse)
74+
rx_converter = Converter(eth_phy_description(phy.dw),
75+
eth_phy_description(dw),
76+
reverse=reverse)
7377
self.submodules += RenameClockDomains(tx_converter, "eth_tx")
7478
self.submodules += RenameClockDomains(rx_converter, "eth_rx")
7579

‎misoclib/com/liteeth/phy/gmii.py

+11-7
Original file line numberDiff line numberDiff line change
@@ -63,10 +63,10 @@ def __init__(self, clock_pads, pads, with_hw_init_reset, mii_mode=0):
6363
self.specials += DDROutput(1, mii_mode, clock_pads.gtx, ClockSignal("eth_tx"))
6464
# XXX Xilinx specific, replace BUFGMUX with a generic clock buffer?
6565
self.specials += Instance("BUFGMUX",
66-
i_I0=self.cd_eth_rx.clk,
67-
i_I1=clock_pads.tx,
68-
i_S=mii_mode,
69-
o_O=self.cd_eth_tx.clk)
66+
i_I0=self.cd_eth_rx.clk,
67+
i_I1=clock_pads.tx,
68+
i_S=mii_mode,
69+
o_O=self.cd_eth_tx.clk)
7070

7171
if with_hw_init_reset:
7272
reset = Signal()
@@ -89,7 +89,11 @@ def __init__(self, clock_pads, pads, with_hw_init_reset, mii_mode=0):
8989
class LiteEthPHYGMII(Module, AutoCSR):
9090
def __init__(self, clock_pads, pads, with_hw_init_reset=True):
9191
self.dw = 8
92-
self.submodules.crg = LiteEthPHYGMIICRG(clock_pads, pads, with_hw_init_reset)
93-
self.submodules.tx = RenameClockDomains(LiteEthPHYGMIITX(pads), "eth_tx")
94-
self.submodules.rx = RenameClockDomains(LiteEthPHYGMIIRX(pads), "eth_rx")
92+
self.submodules.crg = LiteEthPHYGMIICRG(clock_pads,
93+
pads,
94+
with_hw_init_reset)
95+
self.submodules.tx = RenameClockDomains(LiteEthPHYGMIITX(pads),
96+
"eth_tx")
97+
self.submodules.rx = RenameClockDomains(LiteEthPHYGMIIRX(pads),
98+
"eth_rx")
9599
self.sink, self.source = self.tx.sink, self.rx.source

‎misoclib/com/liteeth/phy/mii.py

+4-2
Original file line numberDiff line numberDiff line change
@@ -15,7 +15,8 @@ def __init__(self, pads, pads_register=True):
1515

1616
if hasattr(pads, "tx_er"):
1717
self.sync += pads.tx_er.eq(0)
18-
converter = Converter(converter_description(8), converter_description(4))
18+
converter = Converter(converter_description(8),
19+
converter_description(4))
1920
self.submodules += converter
2021
self.comb += [
2122
converter.sink.stb.eq(sink.stb),
@@ -42,7 +43,8 @@ def __init__(self, pads):
4243
sop = FlipFlop(reset=1)
4344
self.submodules += sop
4445

45-
converter = Converter(converter_description(4), converter_description(8))
46+
converter = Converter(converter_description(4),
47+
converter_description(8))
4648
converter = InsertReset(converter)
4749
self.submodules += converter
4850

‎misoclib/com/liteeth/test/etherbone_tb.py

+4-2
Original file line numberDiff line numberDiff line change
@@ -65,7 +65,8 @@ def gen_simulation(self, selfp):
6565
# test writes
6666
if test_writes:
6767
writes_datas = [j for j in range(16)]
68-
writes = etherbone.EtherboneWrites(base_addr=0x1000, datas=writes_datas)
68+
writes = etherbone.EtherboneWrites(base_addr=0x1000,
69+
datas=writes_datas)
6970
record = etherbone.EtherboneRecord()
7071
record.writes = writes
7172
record.reads = None
@@ -88,7 +89,8 @@ def gen_simulation(self, selfp):
8889
# test reads
8990
if test_reads:
9091
reads_addrs = [0x1000 + 4*j for j in range(16)]
91-
reads = etherbone.EtherboneReads(base_ret_addr=0x1000, addrs=reads_addrs)
92+
reads = etherbone.EtherboneReads(base_ret_addr=0x1000,
93+
addrs=reads_addrs)
9294
record = etherbone.EtherboneRecord()
9395
record.writes = None
9496
record.reads = reads

‎misoclib/com/liteeth/test/model/arp.py

+3-1
Original file line numberDiff line numberDiff line change
@@ -27,7 +27,9 @@ def decode(self):
2727
def encode(self):
2828
header = 0
2929
for k, v in sorted(arp_header.items()):
30-
value = merge_bytes(split_bytes(getattr(self, k), math.ceil(v.width/8)), "little")
30+
value = merge_bytes(split_bytes(getattr(self, k),
31+
math.ceil(v.width/8)),
32+
"little")
3133
header += (value << v.offset+(v.byte*8))
3234
for d in split_bytes(header, arp_header_len):
3335
self.insert(0, d)

‎misoclib/com/liteeth/test/model/etherbone.py

+3-1
Original file line numberDiff line numberDiff line change
@@ -194,7 +194,9 @@ def encode(self):
194194
self.set_reads(self.reads)
195195
header = 0
196196
for k, v in sorted(etherbone_record_header.items()):
197-
value = merge_bytes(split_bytes(getattr(self, k), math.ceil(v.width/8)), "little")
197+
value = merge_bytes(split_bytes(getattr(self, k),
198+
math.ceil(v.width/8)),
199+
"little")
198200
header += (value << v.offset+(v.byte*8))
199201
for d in split_bytes(header, etherbone_record_header_len):
200202
self.insert(0, d)

‎misoclib/com/liteeth/test/model/icmp.py

+3-1
Original file line numberDiff line numberDiff line change
@@ -25,7 +25,9 @@ def decode(self):
2525
def encode(self):
2626
header = 0
2727
for k, v in sorted(icmp_header.items()):
28-
value = merge_bytes(split_bytes(getattr(self, k), math.ceil(v.width/8)), "little")
28+
value = merge_bytes(split_bytes(getattr(self, k),
29+
math.ceil(v.width/8)),
30+
"little")
2931
header += (value << v.offset+(v.byte*8))
3032
for d in split_bytes(header, icmp_header_len):
3133
self.insert(0, d)

‎misoclib/com/liteeth/test/model/ip.py

+3-1
Original file line numberDiff line numberDiff line change
@@ -44,7 +44,9 @@ def decode(self):
4444
def encode(self):
4545
header = 0
4646
for k, v in sorted(ipv4_header.items()):
47-
value = merge_bytes(split_bytes(getattr(self, k), math.ceil(v.width/8)), "little")
47+
value = merge_bytes(split_bytes(getattr(self, k),
48+
math.ceil(v.width/8)),
49+
"little")
4850
header += (value << v.offset+(v.byte*8))
4951
for d in split_bytes(header, ipv4_header_len):
5052
self.insert(0, d)

‎misoclib/com/liteeth/test/model/mac.py

+3-1
Original file line numberDiff line numberDiff line change
@@ -60,7 +60,9 @@ def decode(self):
6060
def encode_header(self):
6161
header = 0
6262
for k, v in sorted(mac_header.items()):
63-
value = merge_bytes(split_bytes(getattr(self, k), math.ceil(v.width/8)), "little")
63+
value = merge_bytes(split_bytes(getattr(self, k),
64+
math.ceil(v.width/8)),
65+
"little")
6466
header += (value << v.offset+(v.byte*8))
6567
for d in split_bytes(header, mac_header_len):
6668
self.insert(0, d)

‎misoclib/com/liteeth/test/model/udp.py

+3-1
Original file line numberDiff line numberDiff line change
@@ -25,7 +25,9 @@ def decode(self):
2525
def encode(self):
2626
header = 0
2727
for k, v in sorted(udp_header.items()):
28-
value = merge_bytes(split_bytes(getattr(self, k), math.ceil(v.width/8)), "little")
28+
value = merge_bytes(split_bytes(getattr(self, k),
29+
math.ceil(v.width/8)),
30+
"little")
2931
header += (value << v.offset+(v.byte*8))
3032
for d in split_bytes(header, udp_header_len):
3133
self.insert(0, d)

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