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base repository: m-labs/misoc
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  • 4 commits
  • 2 files changed
  • 1 contributor

Commits on Apr 12, 2015

  1. liteeth/phy/mii: allow use of MII phy on GMII/MII chips that do not h…

    …ave phy clock provided by the FPGA (tested on KC705)
    enjoy-digital committed Apr 12, 2015
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Showing with 35 additions and 75 deletions.
  1. +1 −0 misoclib/com/liteeth/common.py
  2. +34 −75 misoclib/com/liteeth/phy/mii.py
1 change: 1 addition & 0 deletions misoclib/com/liteeth/common.py
Original file line number Diff line number Diff line change
@@ -139,6 +139,7 @@ def _remove_from_layout(layout, *args):
if not remove:
r.append(f)
return r

def eth_phy_description(dw):
payload_layout = [
("data", dw),
109 changes: 34 additions & 75 deletions misoclib/com/liteeth/phy/mii.py
Original file line number Diff line number Diff line change
@@ -1,100 +1,59 @@
from misoclib.com.liteeth.common import *
from misoclib.com.liteeth.generic import *

def converter_description(dw):
payload_layout = [("data", dw)]
return EndpointDescription(payload_layout, packetized=True)

class LiteEthPHYMIITX(Module):
def __init__(self, pads):
self.sink = sink = Sink(eth_phy_description(8))
###
tx_en_r = Signal()
tx_data_r = Signal(4)
if hasattr(pads, "tx_er"):
self.sync += pads.tx_er.eq(0)
converter = Converter(converter_description(8), converter_description(4))
self.submodules += converter
self.comb += [
converter.sink.stb.eq(sink.stb),
converter.sink.data.eq(sink.data),
sink.ack.eq(converter.sink.ack),
converter.source.ack.eq(1)
]
self.sync += [
pads.tx_er.eq(0),
pads.tx_en.eq(tx_en_r),
pads.tx_data.eq(tx_data_r),
pads.tx_en.eq(converter.source.stb),
pads.tx_data.eq(converter.source.data)
]

fsm = FSM(reset_state="IDLE")
self.submodules += fsm
fsm.act("IDLE",
sink.ack.eq(1),
If(sink.stb & sink.sop,
sink.ack.eq(0),
NextState("SEND_LO")
)
)
fsm.act("SEND_LO",
tx_data_r.eq(sink.data[0:4]),
tx_en_r.eq(1),
NextState("SEND_HI")
)
fsm.act("SEND_HI",
tx_data_r.eq(sink.data[4:8]),
tx_en_r.eq(1),
sink.ack.eq(1),
If(sink.stb & sink.eop,
NextState("IDLE")
).Else(
NextState("SEND_LO")
)
)

class LiteEthPHYMIIRX(Module):
def __init__(self, pads):
self.source = source = Source(eth_phy_description(8))
###
sop = source.sop
set_sop = Signal()
clr_sop = Signal()
self.sync += \
If(clr_sop,
sop.eq(0)
).Elif(set_sop,
sop.eq(1)
)
sop = FlipFlop(reset=1)
self.submodules += sop

lo = Signal(4)
hi = Signal(4)
load_nibble = Signal(2)
self.sync += \
If(load_nibble[0],
lo.eq(pads.rx_data)
).Elif(load_nibble[1],
hi.eq(pads.rx_data)
)
converter = Converter(converter_description(4), converter_description(8))
converter = InsertReset(converter)
self.submodules += converter

self.sync += [
converter.reset.eq(~pads.dv),
converter.sink.stb.eq(1),
converter.sink.data.eq(pads.rx_data)
]
self.comb += [
source.data.eq(Cat(lo, hi))
sop.reset.eq(~pads.dv),
sop.ce.eq(pads.dv),
converter.sink.sop.eq(sop.q),
converter.sink.eop.eq(~pads.dv)
]

fsm = FSM(reset_state="IDLE")
self.submodules += fsm
fsm.act("IDLE",
set_sop.eq(1),
If(pads.dv,
load_nibble.eq(0b01),
NextState("LOAD_HI")
)
)
fsm.act("LOAD_LO",
source.stb.eq(1),
If(pads.dv,
clr_sop.eq(1),
load_nibble.eq(0b01),
NextState("LOAD_HI")
).Else(
source.eop.eq(1),
NextState("IDLE")
)
)
fsm.act("LOAD_HI",
load_nibble.eq(0b10),
NextState("LOAD_LO")
)
self.comb += Record.connect(converter.source, source)

class LiteEthPHYMIICRG(Module, AutoCSR):
def __init__(self, clock_pads, pads, with_hw_init_reset):
self._reset = CSRStorage()
###
self.sync.base50 += clock_pads.phy.eq(~clock_pads.phy)
if hasattr(clock_pads, "phy"):
self.sync.base50 += clock_pads.phy.eq(~clock_pads.phy)

self.clock_domains.cd_eth_rx = ClockDomain()
self.clock_domains.cd_eth_tx = ClockDomain()