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base repository: m-labs/artiq
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  • 4 commits
  • 4 files changed
  • 2 contributors

Commits on Apr 11, 2015

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  3. targets/artiq_kc705: add false path between rsys_clk and rio_clk (red…

    …uce P&R on AMP from 40 minutes to 5 minutes :)
    enjoy-digital authored and sbourdeauducq committed Apr 11, 2015
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Showing with 60 additions and 25 deletions.
  1. +3 −2 soc/runtime/dds.h
  2. +28 −11 soc/targets/artiq_kc705.py
  3. +19 −9 soc/targets/artiq_pipistrello.py
  4. +10 −3 soc/targets/artiq_ppro.py
5 changes: 3 additions & 2 deletions soc/runtime/dds.h
Original file line number Diff line number Diff line change
@@ -2,12 +2,13 @@
#define __DDS_H

#include <hw/common.h>
#include <generated/mem.h>

#define DDS_READ(addr) \
MMPTR(0xb0000000 + (addr)*4)
MMPTR(DDS_BASE + (addr)*4)

#define DDS_WRITE(addr, data) \
MMPTR(0xb0000000 + (addr)*4) = data
MMPTR(DDS_BASE + (addr)*4) = data

#define DDS_FTW0 0x0a
#define DDS_FTW1 0x0b
39 changes: 28 additions & 11 deletions soc/targets/artiq_kc705.py
Original file line number Diff line number Diff line change
@@ -2,6 +2,7 @@
from migen.bank.description import *
from migen.bank import wbgen
from mibuild.generic_platform import *
from mibuild.xilinx.vivado import XilinxVivadoToolchain

from misoclib.com import gpio
from misoclib.soc import mem_decoder
@@ -34,6 +35,11 @@ class _Peripherals(MiniSoC):
"rtiocrg": 13
}
csr_map.update(MiniSoC.csr_map)
mem_map = {
"rtio": 0x20000000, # (shadow @0xa0000000)
"dds": 0x50000000, # (shadow @0xd0000000)
}
mem_map.update(MiniSoC.mem_map)

def __init__(self, platform, cpu_type="or1k", **kwargs):
MiniSoC.__init__(self, platform,
@@ -67,40 +73,51 @@ def __init__(self, platform, cpu_type="or1k", **kwargs):
self.submodules.dds = ad9858.AD9858(dds_pads)
self.comb += dds_pads.fud_n.eq(~fud)

if isinstance(platform.toolchain, XilinxVivadoToolchain):
platform.add_platform_command("""
create_clock -name rsys_clk -period 8.0 [get_nets {rsys_clk}]
create_clock -name rio_clk -period 8.0 [get_nets {rio_clk}]
set_false_path -from [get_clocks rsys_clk] -to [get_clocks rio_clk]
set_false_path -from [get_clocks rio_clk] -to [get_clocks rsys_clk]
""", rsys_clk=self.rtio.cd_rsys.clk, rio_clk=self.rtio.cd_rio.clk)

class UP(_Peripherals):
def __init__(self, *args, **kwargs):
_Peripherals.__init__(self, *args, **kwargs)

rtio_csrs = self.rtio.get_csrs()
self.submodules.rtiowb = wbgen.Bank(rtio_csrs)
self.add_wb_slave(mem_decoder(0xa0000000), self.rtiowb.bus)
self.add_csr_region("rtio", 0xa0000000, 32, rtio_csrs)

self.add_wb_slave(mem_decoder(0xb0000000), self.dds.bus)
self.add_wb_slave(mem_decoder(self.mem_map["rtio"]), self.rtiowb.bus)
self.add_csr_region("rtio", self.mem_map["rtio"] + 0x80000000, 32, rtio_csrs)

self.add_wb_slave(mem_decoder(self.mem_map["dds"]), self.dds.bus)
self.add_memory_region("dds", self.mem_map["dds"] + 0x80000000, 64*4)

class AMP(_Peripherals):
csr_map = {
"kernel_cpu": 14
}
csr_map.update(_Peripherals.csr_map)
mem_map = {
"mailbox": 0x70000000 # (shadow @0xf0000000)
}
mem_map.update(_Peripherals.mem_map)

def __init__(self, platform, *args, **kwargs):
_Peripherals.__init__(self, platform, *args, **kwargs)

self.submodules.kernel_cpu = amp.KernelCPU(
platform, self.sdram.crossbar.get_master())
self.submodules.mailbox = amp.Mailbox()
self.add_wb_slave(mem_decoder(0xd0000000), self.mailbox.i1)
self.kernel_cpu.add_wb_slave(mem_decoder(0xd0000000), self.mailbox.i2)
self.add_wb_slave(mem_decoder(self.mem_map["mailbox"]), self.mailbox.i1)
self.kernel_cpu.add_wb_slave(mem_decoder(self.mem_map["mailbox"]), self.mailbox.i2)

rtio_csrs = self.rtio.get_csrs()
self.submodules.rtiowb = wbgen.Bank(rtio_csrs)
self.kernel_cpu.add_wb_slave(mem_decoder(0xa0000000), self.rtiowb.bus)
self.add_csr_region("rtio", 0xa0000000, 32, rtio_csrs)

self.kernel_cpu.add_wb_slave(mem_decoder(0xb0000000), self.dds.bus)
self.kernel_cpu.add_wb_slave(mem_decoder(self.mem_map["rtio"]), self.rtiowb.bus)
self.add_csr_region("rtio", self.mem_map["rtio"] + 0x80000000, 32, rtio_csrs)

self.kernel_cpu.add_wb_slave(mem_decoder(self.mem_map["dds"]), self.dds.bus)
self.add_memory_region("dds", self.mem_map["dds"] + 0x80000000, 64*4)

default_subtarget = UP
default_subtarget = AMP
28 changes: 19 additions & 9 deletions soc/targets/artiq_pipistrello.py
Original file line number Diff line number Diff line change
@@ -51,6 +51,11 @@ class _Peripherals(BaseSoC):
"rtiocrg": 13
}
csr_map.update(BaseSoC.csr_map)
mem_map = {
"rtio": 0x20000000, # (shadow @0xa0000000)
"dds": 0x50000000, # (shadow @0xd0000000)
}
mem_map.update(MiniSoC.mem_map)

def __init__(self, platform, cpu_type="or1k", **kwargs):
BaseSoC.__init__(self, platform, cpu_type=cpu_type, **kwargs)
@@ -93,33 +98,38 @@ def __init__(self, platform, **kwargs):

rtio_csrs = self.rtio.get_csrs()
self.submodules.rtiowb = wbgen.Bank(rtio_csrs)
self.add_wb_slave(mem_decoder(0xa0000000), self.rtiowb.bus)
self.add_csr_region("rtio", 0xa0000000, 32, rtio_csrs)

self.add_wb_slave(mem_decoder(0xb0000000), self.dds.bus)
self.add_wb_slave(mem_decoder(self.mem_map["rtio"]), self.rtiowb.bus)
self.add_csr_region("rtio", self.mem_map["rtio"] + 0x80000000, 32, rtio_csrs)

self.add_wb_slave(mem_decoder(self.mem_map["dds"]), self.dds.bus)
self.add_memory_region("dds", self.mem_map["dds"] + 0x80000000, 64*4)

class AMP(_Peripherals):
csr_map = {
"kernel_cpu": 14
}
csr_map.update(_Peripherals.csr_map)
mem_map = {
"mailbox": 0x70000000 # (shadow @0xf0000000)
}
mem_map.update(_Peripherals.mem_map)

def __init__(self, platform, *args, **kwargs):
_Peripherals.__init__(self, platform, **kwargs)

self.submodules.kernel_cpu = amp.KernelCPU(
platform, self.sdram.crossbar.get_master())
self.submodules.mailbox = amp.Mailbox()
self.add_wb_slave(mem_decoder(0xd0000000), self.mailbox.i1)
self.kernel_cpu.add_wb_slave(mem_decoder(0xd0000000), self.mailbox.i2)
self.add_wb_slave(mem_decoder(self.mem_map["mailbox"]), self.mailbox.i1)
self.kernel_cpu.add_wb_slave(mem_decoder(self.mem_map["mailbox"]), self.mailbox.i2)

rtio_csrs = self.rtio.get_csrs()
self.submodules.rtiowb = wbgen.Bank(rtio_csrs)
self.kernel_cpu.add_wb_slave(mem_decoder(0xa0000000), self.rtiowb.bus)
self.add_csr_region("rtio", 0xa0000000, 32, rtio_csrs)
self.kernel_cpu.add_wb_slave(mem_decoder(self.mem_map["rtio"]), self.rtiowb.bus)
self.add_csr_region("rtio", self.mem_map["rtio"] + 0x80000000, 32, rtio_csrs)

self.kernel_cpu.add_wb_slave(mem_decoder(0xb0000000), self.dds.bus)
self.kernel_cpu.add_wb_slave(mem_decoder(self.mem_map["dds"]), self.dds.bus)
self.kernel_cpu.add_memory_region("dds", self.mem_map["dds"] + 0x80000000, 64*4)


default_subtarget = UP
13 changes: 10 additions & 3 deletions soc/targets/artiq_ppro.py
Original file line number Diff line number Diff line change
@@ -4,6 +4,7 @@
from mibuild.generic_platform import *

from misoclib.com import gpio
from misoclib.soc import mem_decoder
from misoclib.mem.sdram.core.minicon import MiniconSettings
from targets.ppro import BaseSoC

@@ -59,6 +60,11 @@ class UP(BaseSoC):
"rtiocrg": 13
}
csr_map.update(BaseSoC.csr_map)
mem_map = {
"rtio": 0x20000000, # (shadow @0xa0000000)
"dds": 0x50000000, # (shadow @0xd0000000)
}
mem_map.update(MiniSoC.mem_map)

def __init__(self, platform, cpu_type="or1k",
with_test_gen=False, **kwargs):
@@ -93,15 +99,16 @@ def __init__(self, platform, cpu_type="or1k",

rtio_csrs = self.rtio.get_csrs()
self.submodules.rtiowb = wbgen.Bank(rtio_csrs)
self.add_wb_slave(lambda a: a[26:29] == 2, self.rtiowb.bus)
self.add_csr_region("rtio", 0xa0000000, 32, rtio_csrs)
self.add_wb_slave(mem_decoder(self.mem_map["rtio"]), self.rtiowb.bus)
self.add_csr_region("rtio", self.mem_map["rtio"] + 0x80000000, 32, rtio_csrs)

if with_test_gen:
self.submodules.test_gen = _TestGen(platform.request("ttl", 8))

dds_pads = platform.request("dds")
self.submodules.dds = ad9858.AD9858(dds_pads)
self.add_wb_slave(lambda a: a[26:29] == 3, self.dds.bus)
self.add_wb_slave(mem_decoder(self.mem_map["dds"]), self.dds.bus)
self.add_memory_region("dds", self.mem_map["dds"] + 0x80000000, 64*4)
self.comb += dds_pads.fud_n.eq(~fud)