Skip to content

Commit

Permalink
pipistrello: fix csrs, make AMP default
Browse files Browse the repository at this point in the history
jordens committed Apr 15, 2015
1 parent 9795e83 commit f988ec3
Showing 1 changed file with 3 additions and 3 deletions.
6 changes: 3 additions & 3 deletions soc/targets/artiq_pipistrello.py
Original file line number Diff line number Diff line change
@@ -125,7 +125,7 @@ class UP(_Peripherals):
def __init__(self, platform, **kwargs):
_Peripherals.__init__(self, platform, **kwargs)

rtio_csrs = self.rtio.get_csrs()
rtio_csrs = self.rtio.get_csrs() + self.rtio.get_kernel_csrs()
self.submodules.rtiowb = wbgen.Bank(rtio_csrs)
self.add_wb_slave(mem_decoder(self.mem_map["rtio"]), self.rtiowb.bus)
self.add_csr_region("rtio", self.mem_map["rtio"] + 0x80000000, 32,
@@ -156,7 +156,7 @@ def __init__(self, platform, *args, **kwargs):
self.kernel_cpu.add_wb_slave(mem_decoder(self.mem_map["mailbox"]),
self.mailbox.i2)

rtio_csrs = self.rtio.get_csrs()
rtio_csrs = self.rtio.get_kernel_csrs()
self.submodules.rtiowb = wbgen.Bank(rtio_csrs)
self.kernel_cpu.add_wb_slave(mem_decoder(self.mem_map["rtio"]),
self.rtiowb.bus)
@@ -168,4 +168,4 @@ def __init__(self, platform, *args, **kwargs):
self.add_memory_region("dds", self.mem_map["dds"] + 0x80000000, 64*4)


default_subtarget = UP
default_subtarget = AMP

0 comments on commit f988ec3

Please sign in to comment.