Skip to content
Permalink

Comparing changes

Choose two branches to see what’s changed or to start a new pull request. If you need to, you can also or learn more about diff comparisons.

Open a pull request

Create a new pull request by comparing changes across two branches. If you need to, you can also . Learn more about diff comparisons here.
base repository: m-labs/migen
Failed to load repositories. Confirm that selected base ref is valid, then try again.
Loading
base: 9ca3be0f6cf1
Choose a base ref
...
head repository: m-labs/migen
Failed to load repositories. Confirm that selected head ref is valid, then try again.
Loading
compare: 9e7dc175a448
Choose a head ref
  • 4 commits
  • 3 files changed
  • 1 contributor

Commits on Apr 14, 2015

  1. Adding simple travis-ci build.

    Fixes #10
    mithro authored and sbourdeauducq committed Apr 14, 2015
    Copy the full SHA
    9037114 View commit details
  2. Adding .egg-info to the .gitignore

    mithro authored and sbourdeauducq committed Apr 14, 2015
    Copy the full SHA
    3420798 View commit details
  3. Makefile now uses iverilog-vpi

    From `man iverilog-vpi`;
    > iverilog-vpi is a tool to simplify the compilation of VPI modules for use
    > with Icarus Verilog. It takes on the command line a list of C or C++ source
    > files, and generates as output a linked VPI module.
    
    Fixes #11
    mithro authored and sbourdeauducq committed Apr 14, 2015
    Copy the full SHA
    c3c5ffb View commit details
  4. Using a newer version of iverilog.

    mithro authored and sbourdeauducq committed Apr 14, 2015
    Copy the full SHA
    9e7dc17 View commit details
Showing with 22 additions and 4 deletions.
  1. +1 −0 .gitignore
  2. +15 −0 .travis.yml
  3. +6 −4 vpi/Makefile
1 change: 1 addition & 0 deletions .gitignore
Original file line number Diff line number Diff line change
@@ -1,5 +1,6 @@
__pycache__
*.pyc
*.egg-info/
vpi/*.o
vpi/migensim.vpi
examples/*.vcd
15 changes: 15 additions & 0 deletions .travis.yml
Original file line number Diff line number Diff line change
@@ -0,0 +1,15 @@
language: python
python:
- "3.4"

install:
# Install iverilog package.
- "sudo add-apt-repository -y ppa:mithro/iverilog-backport"
- "sudo apt-get update"
- "sudo apt-get install iverilog"
- "iverilog -v; true"
# Build the vpi module.
- "(cd vpi; make; sudo make install)"

script:
- "python setup.py test"
10 changes: 6 additions & 4 deletions vpi/Makefile
Original file line number Diff line number Diff line change
@@ -1,15 +1,17 @@
INSTDIR=/usr/lib/ivl
INCDIRS=-I/usr/include/iverilog
INSTDIR = $(shell iverilog-vpi --install-dir)

CFLAGS = -Wall -O2 $(CFLAGS_$@)
VPI_CFLAGS := $(shell iverilog-vpi --cflags)

OBJ=ipc.o main.o

all: migensim.vpi

%.o: %.c
$(CC) -fPIC -Wall -O2 -c $(INCDIRS) -o $@ $<
$(CC) $(CFLAGS) $(VPI_CFLAGS) -c $(INCDIRS) -o $@ $<

migensim.vpi: $(OBJ)
$(CC) -shared -o $@ $(OBJ) -lvpi
iverilog-vpi --name=migensim $^

install: migensim.vpi
install -m755 -t $(INSTDIR) $^