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base repository: m-labs/misoc
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head repository: m-labs/misoc
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compare: 204072717949
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  • 12 commits
  • 38 files changed
  • 1 contributor

Commits on Apr 13, 2015

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  3. litesata: pep8 (E302)

    enjoy-digital committed Apr 13, 2015
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  4. litesata: pep8 (E231)

    enjoy-digital committed Apr 13, 2015
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  5. litesata: pep8 (E203)

    enjoy-digital committed Apr 13, 2015
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  6. litesata: pep8 (E401)

    enjoy-digital committed Apr 13, 2015
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  7. litesata: pep8 (E222)

    enjoy-digital committed Apr 13, 2015
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  8. litesata: pep8 (E225)

    enjoy-digital committed Apr 13, 2015
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  9. litesata: pep8 (W292)

    enjoy-digital committed Apr 13, 2015
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  11. litesata: pep8 (E265)

    enjoy-digital committed Apr 13, 2015
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Showing with 4,787 additions and 4,618 deletions.
  1. +11 −11 misoclib/mem/litesata/__init__.py
  2. +276 −259 misoclib/mem/litesata/common.py
  3. +6 −5 misoclib/mem/litesata/core/__init__.py
  4. +252 −248 misoclib/mem/litesata/core/command/__init__.py
  5. +247 −241 misoclib/mem/litesata/core/link/__init__.py
  6. +102 −100 misoclib/mem/litesata/core/link/cont.py
  7. +260 −254 misoclib/mem/litesata/core/link/crc.py
  8. +66 −64 misoclib/mem/litesata/core/link/scrambler.py
  9. +251 −242 misoclib/mem/litesata/core/transport/__init__.py
  10. +109 −102 misoclib/mem/litesata/example_designs/make.py
  11. +22 −21 misoclib/mem/litesata/example_designs/platforms/kc705.py
  12. +15 −14 misoclib/mem/litesata/example_designs/platforms/verilog_backend.py
  13. +151 −147 misoclib/mem/litesata/example_designs/targets/bist.py
  14. +46 −46 misoclib/mem/litesata/example_designs/targets/core.py
  15. +179 −173 misoclib/mem/litesata/example_designs/test/bist.py
  16. +27 −25 misoclib/mem/litesata/example_designs/test/make.py
  17. +58 −58 misoclib/mem/litesata/example_designs/test/test_la.py
  18. +8 −8 misoclib/mem/litesata/example_designs/test/test_regs.py
  19. +37 −35 misoclib/mem/litesata/example_designs/test/tools.py
  20. +24 −23 misoclib/mem/litesata/frontend/arbiter.py
  21. +282 −276 misoclib/mem/litesata/frontend/bist.py
  22. +21 −18 misoclib/mem/litesata/frontend/common.py
  23. +20 −19 misoclib/mem/litesata/frontend/crossbar.py
  24. +18 −17 misoclib/mem/litesata/phy/__init__.py
  25. +143 −139 misoclib/mem/litesata/phy/ctrl.py
  26. +158 −149 misoclib/mem/litesata/phy/datapath.py
  27. +153 −152 misoclib/mem/litesata/phy/k7/crg.py
  28. +847 −843 misoclib/mem/litesata/phy/k7/trx.py
  29. +35 −34 misoclib/mem/litesata/test/bist_tb.py
  30. +81 −76 misoclib/mem/litesata/test/command_tb.py
  31. +130 −119 misoclib/mem/litesata/test/common.py
  32. +80 −76 misoclib/mem/litesata/test/cont_tb.py
  33. +52 −49 misoclib/mem/litesata/test/crc_tb.py
  34. +471 −438 misoclib/mem/litesata/test/hdd.py
  35. +32 −29 misoclib/mem/litesata/test/link_tb.py
  36. +75 −69 misoclib/mem/litesata/test/phy_datapath_tb.py
  37. +42 −39 misoclib/mem/litesata/test/scrambler_tb.py
  38. 0 misoclib/tools/litescope/example_designs/build/.keep_me
22 changes: 11 additions & 11 deletions misoclib/mem/litesata/__init__.py
Original file line number Diff line number Diff line change
@@ -5,17 +5,17 @@

from migen.bank.description import *

class LiteSATA(Module, AutoCSR):
def __init__(self, phy, buffer_depth=2*fis_max_dwords,
with_bist=False, with_bist_csr=False):
# phy
self.phy = phy

# core
self.submodules.core = LiteSATACore(self.phy, buffer_depth)
class LiteSATA(Module, AutoCSR):
def __init__(self, phy, buffer_depth=2*fis_max_dwords,
with_bist=False, with_bist_csr=False):
# phy
self.phy = phy

# frontend
self.submodules.crossbar = LiteSATACrossbar(self.core)
if with_bist:
self.submodules.bist = LiteSATABIST(self.crossbar, with_bist_csr)
# core
self.submodules.core = LiteSATACore(self.phy, buffer_depth)

# frontend
self.submodules.crossbar = LiteSATACrossbar(self.core)
if with_bist:
self.submodules.bist = LiteSATABIST(self.crossbar, with_bist_csr)
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