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platforms/kc705: add PCIe pins
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enjoy-digital committed Apr 16, 2015
1 parent 083d371 commit 1562523
Showing 1 changed file with 37 additions and 0 deletions.
37 changes: 37 additions & 0 deletions mibuild/platforms/kc705.py
Original file line number Diff line number Diff line change
@@ -146,6 +146,43 @@
Subsignal("crs", Pins("R30")),
IOStandard("LVCMOS25")
),

("pcie_x1", 0,
Subsignal("rst_n", Pins("G25"), IOStandard("LVCMOS25")),
Subsignal("clk_p", Pins("U8")),
Subsignal("clk_n", Pins("U7")),
Subsignal("rx_p", Pins("M6")),
Subsignal("rx_n", Pins("M5")),
Subsignal("tx_p", Pins("L4")),
Subsignal("tx_n", Pins("L3"))
),
("pcie_x2", 0,
Subsignal("rst_n", Pins("G25"), IOStandard("LVCMOS25")),
Subsignal("clk_p", Pins("U8")),
Subsignal("clk_n", Pins("U7")),
Subsignal("rx_p", Pins("M6 P6")),
Subsignal("rx_n", Pins("M5 P5")),
Subsignal("tx_p", Pins("L4 M2")),
Subsignal("tx_n", Pins("L3 M1"))
),
("pcie_x4", 0,
Subsignal("rst_n", Pins("G25"), IOStandard("LVCMOS25")),
Subsignal("clk_p", Pins("U8")),
Subsignal("clk_n", Pins("U7")),
Subsignal("rx_p", Pins("M6 P6 R4 T6")),
Subsignal("rx_n", Pins("M5 P5 R3 T5")),
Subsignal("tx_p", Pins("L4 M2 N4 P2")),
Subsignal("tx_n", Pins("L3 M1 N3 P1"))
),
("pcie_x8", 0,
Subsignal("rst_n", Pins("G25"), IOStandard("LVCMOS25")),
Subsignal("clk_p", Pins("U8")),
Subsignal("clk_n", Pins("U7")),
Subsignal("rx_p", Pins("M6 P6 R4 T6 V6 W4 Y6 AA4")),
Subsignal("rx_n", Pins("M5 P5 R3 T5 V5 W3 Y5 AA3")),
Subsignal("tx_p", Pins("L4 M2 N4 P2 T2 U4 V2 Y2")),
Subsignal("tx_n", Pins("L3 M1 N3 P1 T1 U3 V1 Y1"))
)
]

_connectors = [

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